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DBT-RISE-TGC
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adds verilog literal and illegal_instr to asmjit

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Eyck-Alexander Jentzsch 2024-05-18 21:00:21 +02:00
parent fb330cddea
commit a27850f841
2 changed files with 194 additions and 179 deletions
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12
gen_input/templates/asmjit/CORENAME.cpp.gtl
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@ -174,9 +174,17 @@ private:
* end opcode definitions * end opcode definitions
****************************************************************************/ ****************************************************************************/
continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) { continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
x86::Compiler& cc = jh.cc;
cc.comment(fmt::format("illegal_intruction{:#x}:",pc.val).c_str());
this->gen_sync(jh, PRE_SYNC, instr_descr.size());
pc = pc + ((instr & 3) == 3 ? 4 : 2);
gen_instr_prologue(jh);
cc.comment("//behavior:");
gen_instr_epilogue(jh);
this->gen_sync(jh, POST_SYNC, instr_descr.size());
return BRANCH; return BRANCH;
} }
//decoding functionality //decoding functionality
void populate_decoding_tree(decoding_tree_node* root){ void populate_decoding_tree(decoding_tree_node* root){

361
src/vm/asmjit/vm_tgc5c.cpp
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