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DBT-RISE-TGC
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adds verilog literal and illegal_instr to asmjit

This commit is contained in:
Eyck-Alexander Jentzsch 2024-05-18 21:00:21 +02:00
parent fb330cddea
commit a27850f841
2 changed files with 194 additions and 179 deletions
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10
gen_input/templates/asmjit/CORENAME.cpp.gtl
View File

@ -174,9 +174,17 @@ private:
* end opcode definitions * end opcode definitions
****************************************************************************/ ****************************************************************************/
continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) { continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
x86::Compiler& cc = jh.cc;
cc.comment(fmt::format("illegal_intruction{:#x}:",pc.val).c_str());
this->gen_sync(jh, PRE_SYNC, instr_descr.size());
pc = pc + ((instr & 3) == 3 ? 4 : 2);
gen_instr_prologue(jh);
cc.comment("//behavior:");
gen_instr_epilogue(jh);
this->gen_sync(jh, POST_SYNC, instr_descr.size());
return BRANCH; return BRANCH;
} }
//decoding functionality //decoding functionality
void populate_decoding_tree(decoding_tree_node* root){ void populate_decoding_tree(decoding_tree_node* root){

19
src/vm/asmjit/vm_tgc5c.cpp
View File

@ -2826,11 +2826,11 @@ private:
} }
else{ else{
auto res = gen_ext(jh, auto res = gen_ext(jh,
(gen_operation(jh, imul, (gen_operation(jh, imul, gen_ext(jh,
gen_ext(jh, gen_ext(jh,
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), load_reg_from_mem(jh, traits::X0 + rs1), 32, true), 64, true), gen_ext(jh,
gen_ext(jh, gen_ext(jh,
gen_ext(jh, load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true)) load_reg_from_mem(jh, traits::X0 + rs2), 32, true), 64, true))
), 64, true); ), 64, true);
if(rd!=0){ if(rd!=0){
cc.mov(get_ptr_for(jh, traits::X0+ rd), cc.mov(get_ptr_for(jh, traits::X0+ rd),
@ -4340,7 +4340,7 @@ private:
cc.comment("//behavior:"); cc.comment("//behavior:");
/*generate behavior*/ /*generate behavior*/
if(rs1&&rs1<static_cast<uint32_t>(traits::RFS)){ if(rs1&&rs1<static_cast<uint32_t>(traits::RFS)){
auto PC_val_v = gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1%static_cast<uint32_t>(traits::RFS)), ~ 0x1) auto PC_val_v = gen_operation(jh, band, load_reg_from_mem(jh, traits::X0 + rs1%static_cast<uint32_t>(traits::RFS)), ~ 1)
; ;
cc.mov(jh.next_pc, PC_val_v); cc.mov(jh.next_pc, PC_val_v);
cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
@ -4474,7 +4474,7 @@ private:
auto new_pc = load_reg_from_mem(jh, traits::X0 + rs1); auto new_pc = load_reg_from_mem(jh, traits::X0 + rs1);
cc.mov(get_ptr_for(jh, traits::X0+ 1), cc.mov(get_ptr_for(jh, traits::X0+ 1),
(uint32_t)(PC+2)); (uint32_t)(PC+2));
auto PC_val_v = gen_operation(jh, band, new_pc, ~ 0x1) auto PC_val_v = gen_operation(jh, band, new_pc, ~ 1)
; ;
cc.mov(jh.next_pc, PC_val_v); cc.mov(jh.next_pc, PC_val_v);
cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U); cc.mov(get_ptr_for(jh, traits::LAST_BRANCH), 32U);
@ -4607,7 +4607,14 @@ private:
* end opcode definitions * end opcode definitions
****************************************************************************/ ****************************************************************************/
continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) { continuation_e illegal_intruction(virt_addr_t &pc, code_word_t instr, jit_holder& jh ) {
x86::Compiler& cc = jh.cc;
cc.comment(fmt::format("illegal_intruction{:#x}:",pc.val).c_str());
this->gen_sync(jh, PRE_SYNC, instr_descr.size());
pc = pc + ((instr & 3) == 3 ? 4 : 2);
gen_instr_prologue(jh);
cc.comment("//behavior:");
gen_instr_epilogue(jh);
this->gen_sync(jh, POST_SYNC, instr_descr.size());
return BRANCH; return BRANCH;
} }
//decoding functionality //decoding functionality