DBT-RISE
/
DBT-RISE-TGC
13
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

fix pointer mess

This commit is contained in:
Eyck Jentzsch 2022-04-26 15:11:57 +02:00
parent 5f6d462973
commit 9d9008a3a2
11 changed files with 160 additions and 175 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
gen_input/templates/CORENAME.cpp.gtl
View File

@ -33,7 +33,7 @@
def getRegisterSizes(){ def getRegisterSizes(){
def regs = registers.collect{it.size} def regs = registers.collect{it.size}
regs[-1]=64 // correct for NEXT_PC regs[-1]=64 // correct for NEXT_PC
regs+=[32, 32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION //regs+=[32, 32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
return regs return regs
} }
%> %>
@ -51,9 +51,7 @@ constexpr std::array<const char*, ${registers.size}> iss::arch::traits<iss::a
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths; constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_bit_widths;
constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets; constexpr std::array<const uint32_t, ${getRegisterSizes().size}> iss::arch::traits<iss::arch::${coreDef.name.toLowerCase()}>::reg_byte_offsets;
${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() { ${coreDef.name.toLowerCase()}::${coreDef.name.toLowerCase()}() = default;
reg.icount = 0;
}
${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default; ${coreDef.name.toLowerCase()}::~${coreDef.name.toLowerCase()}() = default;
@ -64,8 +62,8 @@ void ${coreDef.name.toLowerCase()}::reset(uint64_t address) {
reg.PC=address; reg.PC=address;
reg.NEXT_PC=reg.PC; reg.NEXT_PC=reg.PC;
reg.PRIV=0x3; reg.PRIV=0x3;
reg.trap_state=0; trap_state=0;
reg.icount=0; icount=0;
} }
uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() { uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {

25
gen_input/templates/CORENAME.h.gtl
View File

@ -37,7 +37,7 @@ def nativeTypeSize(int size){
} }
def getRegisterSizes(){ def getRegisterSizes(){
def regs = registers.collect{nativeTypeSize(it.size)} def regs = registers.collect{nativeTypeSize(it.size)}
regs+=[32,32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION // regs+=[32,32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
return regs return regs
} }
def getRegisterOffsets(){ def getRegisterOffsets(){
@ -91,13 +91,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0}; constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
enum reg_e { enum reg_e {
${registers.collect{it.name}.join(', ')}, NUM_REGS, ${registers.collect{it.name}.join(', ')}, NUM_REGS
TRAP_STATE=NUM_REGS,
PENDING_TRAP,
ICOUNT,
CYCLE,
INSTRET,
INSTRUCTION
}; };
using reg_t = uint${addrDataWidth}_t; using reg_t = uint${addrDataWidth}_t;
@ -142,7 +136,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
uint8_t* get_regs_base_ptr() override; uint8_t* get_regs_base_ptr() override;
inline uint64_t get_icount() { return reg.icount; } inline uint64_t get_icount() { return icount; }
inline bool should_stop() { return interrupt_sim; } inline bool should_stop() { return interrupt_sim; }
@ -160,7 +154,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; } inline uint32_t get_last_branch() { return last_branch; }
#pragma pack(push, 1) #pragma pack(push, 1)
@ -168,12 +162,13 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
registers.each { reg -> if(reg.size>0) {%> registers.each { reg -> if(reg.size>0) {%>
uint${byteSize(reg.size)}_t ${reg.name} = 0;<% uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
}}%> }}%>
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0;
uint64_t instret = 0;
uint32_t instruction = 0;
uint32_t last_branch;
} reg; } reg;
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0;
uint64_t cycle = 0;
uint64_t instret = 0;
uint32_t instruction = 0;
uint32_t last_branch = 0;
#pragma pack(pop) #pragma pack(pop)
std::array<address_type, 4> addr_mode; std::array<address_type, 4> addr_mode;

43
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@ -121,7 +121,7 @@ protected:
inline void raise(uint16_t trap_id, uint16_t cause){ inline void raise(uint16_t trap_id, uint16_t cause){
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id; auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val; this->core.trap_state = trap_val;
this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max(); this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
} }
@ -141,39 +141,39 @@ protected:
T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;} T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){ inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint8_t>(space, addr); auto ret = super::template read_mem<uint8_t>(space, addr);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
return ret; return ret;
} }
inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){ inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint16_t>(space, addr); auto ret = super::template read_mem<uint16_t>(space, addr);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
return ret; return ret;
} }
inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){ inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint32_t>(space, addr); auto ret = super::template read_mem<uint32_t>(space, addr);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
return ret; return ret;
} }
inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){ inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint64_t>(space, addr); auto ret = super::template read_mem<uint64_t>(space, addr);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
return ret; return ret;
} }
inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){ inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
super::write_mem(space, addr, data); super::write_mem(space, addr, data);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
} }
inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){ inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
super::write_mem(space, addr, data); super::write_mem(space, addr, data);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
} }
inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){ inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
super::write_mem(space, addr, data); super::write_mem(space, addr, data);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
} }
inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){ inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
super::write_mem(space, addr, data); super::write_mem(space, addr, data);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
} }
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type> template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
inline S sext(U from) { inline S sext(U from) {
@ -278,16 +278,15 @@ typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t
template <typename ARCH> template <typename ARCH>
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
auto pc=start; auto pc=start;
auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]); auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]); auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]); auto& trap_state = this->core.trap_state;
auto* icount = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]); auto& icount = this->core.icount;
auto* instret = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]); auto& cycle = this->core.cycle;
auto *const instruction = reinterpret_cast<code_word_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRUCTION]); auto& instret = this->core.instret;
auto& instr = this->core.instruction;
// we fetch at max 4 byte, alignment is 2 // we fetch at max 4 byte, alignment is 2
auto *const data = reinterpret_cast<uint8_t*>(instruction); auto *const data = reinterpret_cast<uint8_t*>(&instr);
auto& instr = *instruction;
while(!this->core.should_stop() && while(!this->core.should_stop() &&
!(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){ !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
@ -329,16 +328,16 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
process_spawn_blocks(); process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id)); if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
// trap check // trap check
if(*trap_state!=0){ if(trap_state!=0){
super::core.enter_trap(*trap_state, pc.val, instr); super::core.enter_trap(trap_state, pc.val, instr);
} else { } else {
(*icount)++; icount++;
(*instret)++; instret++;
} }
(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++; cycle++;
pc.val=*NEXT_PC; pc.val=*NEXT_PC;
this->core.reg.PC = this->core.reg.NEXT_PC; this->core.reg.PC = this->core.reg.NEXT_PC;
this->core.reg.trap_state = this->core.reg.pending_trap; this->core.trap_state = this->core.pending_trap;
} }
} }
return pc; return pc;

56
incl/iss/arch/riscv_hart_m_p.h
View File

@ -203,7 +203,7 @@ public:
void disass_output(uint64_t pc, const std::string instr) override { void disass_output(uint64_t pc, const std::string instr) override {
CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]", CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]",
pc, instr, (reg_t)state.mstatus, this->reg.icount + cycle_offset); pc, instr, (reg_t)state.mstatus, this->icount + cycle_offset);
}; };
iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; } iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@ -239,11 +239,11 @@ protected:
uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }; uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
uint64_t get_instr_word() override { return arch.reg.instruction; } uint64_t get_instr_word() override { return arch.instruction; }
uint64_t get_instr_count() { return arch.reg.icount; } uint64_t get_instr_count() { return arch.icount; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; } uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }; void set_curr_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
@ -568,13 +568,13 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) { if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
fault_data = addr; fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr); if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31); // issue trap 0 this->trap_state = (1 << 31); // issue trap 0
return iss::Err; return iss::Err;
} }
try { try {
auto alignment = access == iss::access_type::FETCH? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length; auto alignment = access == iss::access_type::FETCH? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
if(alignment>1 && (addr&(alignment-1))){ if(alignment>1 && (addr&(alignment-1))){
this->reg.trap_state = 1<<31 | 4<<16; this->trap_state = 1<<31 | 4<<16;
fault_data=addr; fault_data=addr;
return iss::Err; return iss::Err;
} }
@ -593,12 +593,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
res = read_mem( phys_addr, length, data); res = read_mem( phys_addr, length, data);
} }
if (unlikely(res != iss::Ok)){ if (unlikely(res != iss::Ok)){
this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
fault_data=addr; fault_data=addr;
} }
return res; return res;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -624,7 +624,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
} }
return iss::Ok; return iss::Ok;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -662,12 +662,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) { if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
fault_data = addr; fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr); if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31); // issue trap 0 this->trap_state = (1 << 31); // issue trap 0
return iss::Err; return iss::Err;
} }
try { try {
if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){ if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
this->reg.trap_state = 1<<31 | 6<<16; this->trap_state = 1<<31 | 6<<16;
fault_data=addr; fault_data=addr;
return iss::Err; return iss::Err;
} }
@ -686,12 +686,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
res = write_mem( phys_addr, length, data); res = write_mem( phys_addr, length, data);
} }
if (unlikely(res != iss::Ok)) { if (unlikely(res != iss::Ok)) {
this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr; fault_data=addr;
} }
return res; return res;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -751,7 +751,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
} }
return iss::Ok; return iss::Ok;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -797,7 +797,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) {
auto cycle_val = this->reg.icount + cycle_offset; auto cycle_val = this->icount + cycle_offset;
if (addr == mcycle) { if (addr == mcycle) {
val = static_cast<reg_t>(cycle_val); val = static_cast<reg_t>(cycle_val);
} else if (addr == mcycleh) { } else if (addr == mcycleh) {
@ -819,16 +819,16 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff); mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
} }
} }
cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around cycle_offset = mcycle_csr-this->icount; // TODO: relying on wrap-around
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_instret(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_instret(unsigned addr, reg_t &val) {
if ((addr&0xff) == (minstret&0xff)) { if ((addr&0xff) == (minstret&0xff)) {
val = static_cast<reg_t>(this->reg.instret); val = static_cast<reg_t>(this->instret);
} else if ((addr&0xff) == (minstreth&0xff)) { } else if ((addr&0xff) == (minstreth&0xff)) {
if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err; if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
val = static_cast<reg_t>(this->reg.instret >> 32); val = static_cast<reg_t>(this->instret >> 32);
} }
return iss::Ok; return iss::Ok;
} }
@ -837,20 +837,20 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
if (sizeof(typename traits<BASE>::reg_t) != 4) { if (sizeof(typename traits<BASE>::reg_t) != 4) {
if ((addr&0xff) == (minstreth&0xff)) if ((addr&0xff) == (minstreth&0xff))
return iss::Err; return iss::Err;
this->reg.instret = static_cast<uint64_t>(val); this->instret = static_cast<uint64_t>(val);
} else { } else {
if ((addr&0xff) == (minstret&0xff)) { if ((addr&0xff) == (minstret&0xff)) {
this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val; this->instret = (this->instret & 0xffffffff00000000) + val;
} else { } else {
this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff); this->instret = (static_cast<uint64_t>(val)<<32) + (this->instret & 0xffffffff);
} }
} }
this->reg.instret--; this->instret--;
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) {
uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052; uint64_t time_val = this->icount / (100000000 / 32768 - 1); //-> ~3052;
if (addr == time) { if (addr == time) {
val = static_cast<reg_t>(time_val); val = static_cast<reg_t>(time_val);
} else if (addr == timeh) { } else if (addr == timeh) {
@ -969,7 +969,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned len
const mem_type::page_type &p = mem(paddr.val / mem.page_size); const mem_type::page_type &p = mem(paddr.val / mem.page_size);
uint64_t offs = paddr.val & mem.page_addr_mask; uint64_t offs = paddr.val & mem.page_addr_mask;
std::copy(p.data() + offs, p.data() + offs + length, data); std::copy(p.data() + offs, p.data() + offs + length, data);
if (this->reg.icount > 30000) data[3] |= 0x80; if (this->icount > 30000) data[3] |= 0x80;
} break; } break;
default: { default: {
for(auto offs=0U; offs<length; ++offs) { for(auto offs=0U; offs<length; ++offs) {
@ -1029,7 +1029,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned le
LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
<< "), stopping simulation"; << "), stopping simulation";
} }
this->reg.trap_state=std::numeric_limits<uint32_t>::max(); this->trap_state=std::numeric_limits<uint32_t>::max();
this->interrupt_sim=hostvar; this->interrupt_sim=hostvar;
break; break;
//throw(iss::simulation_stopped(hostvar)); //throw(iss::simulation_stopped(hostvar));
@ -1117,7 +1117,7 @@ template <typename BASE, features_e FEAT> void riscv_hart_m_p<BASE, FEAT>::check
enabled_interrupts >>= 1; enabled_interrupts >>= 1;
res++; res++;
} }
this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id this->pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
} }
} }
@ -1165,7 +1165,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
fault_data = 0; fault_data = 0;
} else { } else {
csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt csr[mepc] = this->reg.NEXT_PC & get_pc_mask(); // store next address if interrupt
this->reg.pending_trap = 0; this->pending_trap = 0;
} }
csr[mcause] = (trap_id << (traits<BASE>::XLEN-1)) + cause; csr[mcause] = (trap_id << (traits<BASE>::XLEN-1)) + cause;
// update mstatus // update mstatus
@ -1187,7 +1187,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_m_p<BASE, FEAT>::e
if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause; if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
// reset trap state // reset trap state
this->reg.PRIV = new_priv; this->reg.PRIV = new_priv;
this->reg.trap_state = 0; this->trap_state = 0;
std::array<char, 32> buffer; std::array<char, 32> buffer;
#if defined(_MSC_VER) #if defined(_MSC_VER)
sprintf(buffer.data(), "0x%016llx", addr); sprintf(buffer.data(), "0x%016llx", addr);

46
incl/iss/arch/riscv_hart_msu_vp.h
View File

@ -307,7 +307,7 @@ public:
void disass_output(uint64_t pc, const std::string instr) override { void disass_output(uint64_t pc, const std::string instr) override {
CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]",
pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.ccount + cycle_offset); pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->icount + cycle_offset);
}; };
iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; } iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@ -610,7 +610,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) { if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
fault_data = addr; fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr); if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31); // issue trap 0 this->trap_state = (1 << 31); // issue trap 0
return iss::Err; return iss::Err;
} }
try { try {
@ -629,12 +629,12 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data): read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data); read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
if (unlikely(res != iss::Ok)){ if (unlikely(res != iss::Ok)){
this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
fault_data=addr; fault_data=addr;
} }
return res; return res;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -650,7 +650,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
case 3: { // SFENCE:VMA upper case 3: { // SFENCE:VMA upper
auto tvm = state.mstatus.TVM; auto tvm = state.mstatus.TVM;
if (this->reg.PRIV == PRIV_S & tvm != 0) { if (this->reg.PRIV == PRIV_S & tvm != 0) {
this->reg.trap_state = (1 << 31) | (2 << 16); this->trap_state = (1 << 31) | (2 << 16);
this->fault_data = this->reg.PC; this->fault_data = this->reg.PC;
return iss::Err; return iss::Err;
} }
@ -671,7 +671,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
} }
return iss::Ok; return iss::Ok;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -709,7 +709,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) { if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
fault_data = addr; fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr); if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31); // issue trap 0 this->trap_state = (1 << 31); // issue trap 0
return iss::Err; return iss::Err;
} }
try { try {
@ -728,12 +728,12 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
write_mem(phys_addr_t{access, space, addr}, length, data): write_mem(phys_addr_t{access, space, addr}, length, data):
write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data); write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
if (unlikely(res != iss::Ok)) { if (unlikely(res != iss::Ok)) {
this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr; fault_data=addr;
} }
return res; return res;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -782,7 +782,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
ptw.clear(); ptw.clear();
auto tvm = state.mstatus.TVM; auto tvm = state.mstatus.TVM;
if (this->reg.PRIV == PRIV_S & tvm != 0) { if (this->reg.PRIV == PRIV_S & tvm != 0) {
this->reg.trap_state = (1 << 31) | (2 << 16); this->trap_state = (1 << 31) | (2 << 16);
this->fault_data = this->reg.PC; this->fault_data = this->reg.PC;
return iss::Err; return iss::Err;
} }
@ -798,7 +798,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
} }
return iss::Ok; return iss::Ok;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -844,7 +844,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_reg(unsigned
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) { template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_cycle(unsigned addr, reg_t &val) {
auto cycle_val = this->reg.icount + cycle_offset; auto cycle_val = this->icount + cycle_offset;
if (addr == mcycle) { if (addr == mcycle) {
val = static_cast<reg_t>(cycle_val); val = static_cast<reg_t>(cycle_val);
} else if (addr == mcycleh) { } else if (addr == mcycleh) {
@ -866,7 +866,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_cycle(unsigned
mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff); mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
} }
} }
cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around cycle_offset = mcycle_csr-this->icount; // TODO: relying on wrap-around
return iss::Ok; return iss::Ok;
} }
@ -897,7 +897,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_instret(unsigne
} }
template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) { template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned addr, reg_t &val) {
uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052; uint64_t time_val = this->icount / (100000000 / 32768 - 1); //-> ~3052;
if (addr == time) { if (addr == time) {
val = static_cast<reg_t>(time_val); val = static_cast<reg_t>(time_val);
} else if (addr == timeh) { } else if (addr == timeh) {
@ -966,7 +966,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_epc(unsigned
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_satp(unsigned addr, reg_t &val) { template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_satp(unsigned addr, reg_t &val) {
reg_t tvm = state.mstatus.TVM; reg_t tvm = state.mstatus.TVM;
if (this->reg.PRIV == PRIV_S & tvm != 0) { if (this->reg.PRIV == PRIV_S & tvm != 0) {
this->reg.trap_state = (1 << 31) | (2 << 16); this->trap_state = (1 << 31) | (2 << 16);
this->fault_data = this->reg.PC; this->fault_data = this->reg.PC;
return iss::Err; return iss::Err;
} }
@ -977,7 +977,7 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_satp(unsigned
template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_satp(unsigned addr, reg_t val) { template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_satp(unsigned addr, reg_t val) {
reg_t tvm = state.mstatus.TVM; reg_t tvm = state.mstatus.TVM;
if (this->reg.PRIV == PRIV_S & tvm != 0) { if (this->reg.PRIV == PRIV_S & tvm != 0) {
this->reg.trap_state = (1 << 31) | (2 << 16); this->trap_state = (1 << 31) | (2 << 16);
this->fault_data = this->reg.PC; this->fault_data = this->reg.PC;
return iss::Err; return iss::Err;
} }
@ -1033,7 +1033,7 @@ iss::status riscv_hart_msu_vp<BASE>::read_mem(phys_addr_t paddr, unsigned length
const mem_type::page_type &p = mem(paddr.val / mem.page_size); const mem_type::page_type &p = mem(paddr.val / mem.page_size);
uint64_t offs = paddr.val & mem.page_addr_mask; uint64_t offs = paddr.val & mem.page_addr_mask;
std::copy(p.data() + offs, p.data() + offs + length, data); std::copy(p.data() + offs, p.data() + offs + length, data);
if (this->reg.icount > 30000) data[3] |= 0x80; if (this->icount > 30000) data[3] |= 0x80;
} break; } break;
default: { default: {
for(auto offs=0U; offs<length; ++offs) { for(auto offs=0U; offs<length; ++offs) {
@ -1093,7 +1093,7 @@ iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned lengt
LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
<< "), stopping simulation"; << "), stopping simulation";
} }
this->reg.trap_state=std::numeric_limits<uint32_t>::max(); this->trap_state=std::numeric_limits<uint32_t>::max();
this->interrupt_sim=hostvar; this->interrupt_sim=hostvar;
break; break;
//throw(iss::simulation_stopped(hostvar)); //throw(iss::simulation_stopped(hostvar));
@ -1162,7 +1162,7 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::check_interrupt() {
if (enabled_interrupts != 0) { if (enabled_interrupts != 0) {
int res = 0; int res = 0;
while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++; while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id this->pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
} }
} }
@ -1306,7 +1306,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
if (cur_priv != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0) if (cur_priv != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0)
new_priv = (csr[sideleg] >> cause) & 0x1 ? PRIV_U : PRIV_S; new_priv = (csr[sideleg] >> cause) & 0x1 ? PRIV_U : PRIV_S;
csr[uepc | (new_priv << 8)] = this->reg.NEXT_PC; // store next address if interrupt csr[uepc | (new_priv << 8)] = this->reg.NEXT_PC; // store next address if interrupt
this->reg.pending_trap = 0; this->pending_trap = 0;
} }
size_t adr = ucause | (new_priv << 8); size_t adr = ucause | (new_priv << 8);
csr[adr] = (trap_id << 31) + cause; csr[adr] = (trap_id << 31) + cause;
@ -1351,7 +1351,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
<< lvl[cur_priv] << " to " << lvl[new_priv]; << lvl[cur_priv] << " to " << lvl[new_priv];
// reset trap state // reset trap state
this->reg.PRIV = new_priv; this->reg.PRIV = new_priv;
this->reg.trap_state = 0; this->trap_state = 0;
update_vm_info(); update_vm_info();
return this->reg.NEXT_PC; return this->reg.NEXT_PC;
} }
@ -1363,7 +1363,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::leave_trap(uint64_t f
auto tsr = state.mstatus.TSR; auto tsr = state.mstatus.TSR;
if (cur_priv == PRIV_S && inst_priv == PRIV_S && tsr != 0) { if (cur_priv == PRIV_S && inst_priv == PRIV_S && tsr != 0) {
this->reg.trap_state = (1 << 31) | (2 << 16); this->trap_state = (1 << 31) | (2 << 16);
this->fault_data = this->reg.PC; this->fault_data = this->reg.PC;
return this->reg.PC; return this->reg.PC;
} }
@ -1402,7 +1402,7 @@ template <typename BASE> void riscv_hart_msu_vp<BASE>::wait_until(uint64_t flags
auto status = state.mstatus; auto status = state.mstatus;
auto tw = status.TW; auto tw = status.TW;
if (this->reg.PRIV == PRIV_S && tw != 0) { if (this->reg.PRIV == PRIV_S && tw != 0) {
this->reg.trap_state = (1 << 31) | (2 << 16); this->trap_state = (1 << 31) | (2 << 16);
this->fault_data = this->reg.PC; this->fault_data = this->reg.PC;
} }
} }

58
incl/iss/arch/riscv_hart_mu_p.h
View File

@ -218,7 +218,7 @@ public:
void disass_output(uint64_t pc, const std::string instr) override { void disass_output(uint64_t pc, const std::string instr) override {
CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]", CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]",
pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->reg.icount + cycle_offset); pc, instr, lvl[this->reg.PRIV], (reg_t)state.mstatus, this->icount + cycle_offset);
}; };
iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; } iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
@ -704,20 +704,20 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) { if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
fault_data = addr; fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr); if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1 this->trap_state = (1 << 31) | ((access==access_type::FETCH?1:5) << 16); // issue trap 1
return iss::Err; return iss::Err;
} }
} }
if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) { if (unlikely((access == iss::access_type::FETCH || access == iss::access_type::DEBUG_FETCH) && (addr & 0x1) == 1)) {
fault_data = addr; fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr); if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31); // issue trap 0 this->trap_state = (1 << 31); // issue trap 0
return iss::Err; return iss::Err;
} }
try { try {
auto alignment = access == iss::access_type::FETCH? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length; auto alignment = access == iss::access_type::FETCH? (traits<BASE>::MISA_VAL&0x100? 2 : 4) : length;
if(alignment>1 && (addr&(alignment-1))){ if(alignment>1 && (addr&(alignment-1))){
this->reg.trap_state = 1<<31 | 4<<16; this->trap_state = 1<<31 | 4<<16;
fault_data=addr; fault_data=addr;
return iss::Err; return iss::Err;
} }
@ -736,12 +736,12 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
res = read_mem( phys_addr, length, data); res = read_mem( phys_addr, length, data);
} }
if (unlikely(res != iss::Ok)){ if (unlikely(res != iss::Ok)){
this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault this->trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
fault_data=addr; fault_data=addr;
} }
return res; return res;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -767,7 +767,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
} }
return iss::Ok; return iss::Ok;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -806,19 +806,19 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) { if(!pmp_check(access, addr, length) && (access&access_type::DEBUG) != access_type::DEBUG) {
fault_data = addr; fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr); if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 1 this->trap_state = (1 << 31) | (7 << 16); // issue trap 1
return iss::Err; return iss::Err;
} }
} }
if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) { if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
fault_data = addr; fault_data = addr;
if (access && iss::access_type::DEBUG) throw trap_access(0, addr); if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
this->reg.trap_state = (1 << 31); // issue trap 0 this->trap_state = (1 << 31); // issue trap 0
return iss::Err; return iss::Err;
} }
try { try {
if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){ if(length>1 && (addr&(length-1)) && (access&access_type::DEBUG) != access_type::DEBUG){
this->reg.trap_state = 1<<31 | 6<<16; this->trap_state = 1<<31 | 6<<16;
fault_data=addr; fault_data=addr;
return iss::Err; return iss::Err;
} }
@ -837,12 +837,12 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
res = write_mem( phys_addr, length, data); res = write_mem( phys_addr, length, data);
} }
if (unlikely(res != iss::Ok)) { if (unlikely(res != iss::Ok)) {
this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) this->trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr; fault_data=addr;
} }
return res; return res;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -902,7 +902,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
} }
return iss::Ok; return iss::Ok;
} catch (trap_access &ta) { } catch (trap_access &ta) {
this->reg.trap_state = (1 << 31) | ta.id; this->trap_state = (1 << 31) | ta.id;
fault_data=ta.addr; fault_data=ta.addr;
return iss::Err; return iss::Err;
} }
@ -948,7 +948,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_cycle(unsigned addr, reg_t &val) {
auto cycle_val = this->reg.icount + cycle_offset; auto cycle_val = this->icount + cycle_offset;
if (addr == mcycle) { if (addr == mcycle) {
val = static_cast<reg_t>(cycle_val); val = static_cast<reg_t>(cycle_val);
} else if (addr == mcycleh) { } else if (addr == mcycleh) {
@ -970,16 +970,16 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff); mcycle_csr = (static_cast<uint64_t>(val)<<32) + (mcycle_csr & 0xffffffff);
} }
} }
cycle_offset = mcycle_csr-this->reg.icount; // TODO: relying on wrap-around cycle_offset = mcycle_csr-this->icount; // TODO: relying on wrap-around
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_instret(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_instret(unsigned addr, reg_t &val) {
if ((addr&0xff) == (minstret&0xff)) { if ((addr&0xff) == (minstret&0xff)) {
val = static_cast<reg_t>(this->reg.instret); val = static_cast<reg_t>(this->instret);
} else if ((addr&0xff) == (minstreth&0xff)) { } else if ((addr&0xff) == (minstreth&0xff)) {
if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err; if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
val = static_cast<reg_t>(this->reg.instret >> 32); val = static_cast<reg_t>(this->instret >> 32);
} }
return iss::Ok; return iss::Ok;
} }
@ -988,20 +988,20 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
if (sizeof(typename traits<BASE>::reg_t) != 4) { if (sizeof(typename traits<BASE>::reg_t) != 4) {
if ((addr&0xff) == (minstreth&0xff)) if ((addr&0xff) == (minstreth&0xff))
return iss::Err; return iss::Err;
this->reg.instret = static_cast<uint64_t>(val); this->instret = static_cast<uint64_t>(val);
} else { } else {
if ((addr&0xff) == (minstret&0xff)) { if ((addr&0xff) == (minstret&0xff)) {
this->reg.instret = (this->reg.instret & 0xffffffff00000000) + val; this->instret = (this->instret & 0xffffffff00000000) + val;
} else { } else {
this->reg.instret = (static_cast<uint64_t>(val)<<32) + (this->reg.instret & 0xffffffff); this->instret = (static_cast<uint64_t>(val)<<32) + (this->instret & 0xffffffff);
} }
} }
this->reg.instret--; this->instret--;
return iss::Ok; return iss::Ok;
} }
template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) { template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT>::read_time(unsigned addr, reg_t &val) {
uint64_t time_val = this->reg.icount / (100000000 / 32768 - 1); //-> ~3052; uint64_t time_val = this->icount / (100000000 / 32768 - 1); //-> ~3052;
if (addr == time) { if (addr == time) {
val = static_cast<reg_t>(time_val); val = static_cast<reg_t>(time_val);
} else if (addr == timeh) { } else if (addr == timeh) {
@ -1137,7 +1137,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned le
const mem_type::page_type &p = mem(paddr.val / mem.page_size); const mem_type::page_type &p = mem(paddr.val / mem.page_size);
uint64_t offs = paddr.val & mem.page_addr_mask; uint64_t offs = paddr.val & mem.page_addr_mask;
std::copy(p.data() + offs, p.data() + offs + length, data); std::copy(p.data() + offs, p.data() + offs + length, data);
if (this->reg.icount > 30000) data[3] |= 0x80; if (this->icount > 30000) data[3] |= 0x80;
} break; } break;
default: { default: {
for(auto offs=0U; offs<length; ++offs) { for(auto offs=0U; offs<length; ++offs) {
@ -1196,7 +1196,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_mem(phys_addr_t paddr, unsigned l
LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
<< "), stopping simulation"; << "), stopping simulation";
} }
this->reg.trap_state=std::numeric_limits<uint32_t>::max(); this->trap_state=std::numeric_limits<uint32_t>::max();
this->interrupt_sim=hostvar; this->interrupt_sim=hostvar;
break; break;
//throw(iss::simulation_stopped(hostvar)); //throw(iss::simulation_stopped(hostvar));
@ -1284,14 +1284,14 @@ template <typename BASE, features_e FEAT> void riscv_hart_mu_p<BASE, FEAT>::chec
enabled_interrupts >>= 1; enabled_interrupts >>= 1;
res++; res++;
} }
this->reg.pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id this->pending_trap = res << 16 | 1; // 0x80 << 24 | (cause << 16) | trap_id
} }
} }
template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) { template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::enter_trap(uint64_t flags, uint64_t addr, uint64_t instr) {
// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0] // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
// calculate and write mcause val // calculate and write mcause val
if(flags==std::numeric_limits<uint64_t>::max()) flags=this->reg.trap_state; if(flags==std::numeric_limits<uint64_t>::max()) flags=this->trap_state;
auto trap_id = bit_sub<0, 16>(flags); auto trap_id = bit_sub<0, 16>(flags);
auto cause = bit_sub<16, 15>(flags); auto cause = bit_sub<16, 15>(flags);
if (trap_id == 0 && cause == 11) cause = 0x8 + this->reg.PRIV; // adjust environment call cause if (trap_id == 0 && cause == 11) cause = 0x8 + this->reg.PRIV; // adjust environment call cause
@ -1338,7 +1338,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
if (this->reg.PRIV != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0) if (this->reg.PRIV != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0)
new_priv = PRIV_U; new_priv = PRIV_U;
csr[uepc | (new_priv << 8)] = this->reg.NEXT_PC; // store next address if interrupt csr[uepc | (new_priv << 8)] = this->reg.NEXT_PC; // store next address if interrupt
this->reg.pending_trap = 0; this->pending_trap = 0;
} }
size_t adr = ucause | (new_priv << 8); size_t adr = ucause | (new_priv << 8);
csr[adr] = (trap_id << (traits<BASE>::XLEN-1)) + cause; csr[adr] = (trap_id << (traits<BASE>::XLEN-1)) + cause;
@ -1378,7 +1378,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
<< lvl[this->reg.PRIV] << " to " << lvl[new_priv]; << lvl[this->reg.PRIV] << " to " << lvl[new_priv];
// reset trap state // reset trap state
this->reg.PRIV = new_priv; this->reg.PRIV = new_priv;
this->reg.trap_state = 0; this->trap_state = 0;
return this->reg.NEXT_PC; return this->reg.NEXT_PC;
} }
@ -1387,7 +1387,7 @@ template <typename BASE, features_e FEAT> uint64_t riscv_hart_mu_p<BASE, FEAT>::
auto inst_priv = (flags & 0x3)? 3:0; auto inst_priv = (flags & 0x3)? 3:0;
if(inst_priv>cur_priv){ if(inst_priv>cur_priv){
auto trap_val = 0x80ULL << 24 | (2 << 16); // illegal instruction auto trap_val = 0x80ULL << 24 | (2 << 16); // illegal instruction
this->reg.trap_state = trap_val; this->trap_state = trap_val;
this->reg.NEXT_PC = std::numeric_limits<uint32_t>::max(); this->reg.NEXT_PC = std::numeric_limits<uint32_t>::max();
} else { } else {
auto status = state.mstatus; auto status = state.mstatus;

31
incl/iss/arch/tgc_c.h
View File

@ -58,13 +58,7 @@ template <> struct traits<tgc_c> {
constexpr static unsigned FP_REGS_SIZE = 0; constexpr static unsigned FP_REGS_SIZE = 0;
enum reg_e { enum reg_e {
X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS, X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X12, X13, X14, X15, X16, X17, X18, X19, X20, X21, X22, X23, X24, X25, X26, X27, X28, X29, X30, X31, PC, NEXT_PC, PRIV, DPC, NUM_REGS
TRAP_STATE=NUM_REGS,
PENDING_TRAP,
ICOUNT,
CYCLE,
INSTRET,
INSTRUCTION
}; };
using reg_t = uint32_t; using reg_t = uint32_t;
@ -77,11 +71,11 @@ template <> struct traits<tgc_c> {
using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>; using phys_addr_t = iss::typed_addr_t<iss::address_type::PHYSICAL>;
static constexpr std::array<const uint32_t, 42> reg_bit_widths{ static constexpr std::array<const uint32_t, 36> reg_bit_widths{
{32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32,32,32,64,64,64,32}}; {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,8,32}};
static constexpr std::array<const uint32_t, 42> reg_byte_offsets{ static constexpr std::array<const uint32_t, 36> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173}}; {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137}};
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
@ -198,7 +192,7 @@ struct tgc_c: public arch_if {
uint8_t* get_regs_base_ptr() override; uint8_t* get_regs_base_ptr() override;
inline uint64_t get_icount() { return reg.icount; } inline uint64_t get_icount() { return icount; }
inline bool should_stop() { return interrupt_sim; } inline bool should_stop() { return interrupt_sim; }
@ -216,7 +210,7 @@ struct tgc_c: public arch_if {
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
inline uint32_t get_last_branch() { return reg.last_branch; } inline uint32_t get_last_branch() { return last_branch; }
#pragma pack(push, 1) #pragma pack(push, 1)
@ -257,12 +251,13 @@ struct tgc_c: public arch_if {
uint32_t NEXT_PC = 0; uint32_t NEXT_PC = 0;
uint8_t PRIV = 0; uint8_t PRIV = 0;
uint32_t DPC = 0; uint32_t DPC = 0;
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0;
uint64_t instret = 0;
uint32_t instruction = 0;
uint32_t last_branch;
} reg; } reg;
uint32_t trap_state = 0, pending_trap = 0;
uint64_t icount = 0;
uint64_t cycle = 0;
uint64_t instret = 0;
uint32_t instruction = 0;
uint32_t last_branch = 0;
#pragma pack(pop) #pragma pack(pop)
std::array<address_type, 4> addr_mode; std::array<address_type, 4> addr_mode;

12
src/iss/tgc_c.cpp
View File

@ -41,12 +41,10 @@ using namespace iss::arch;
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_names; constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_names;
constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_aliases; constexpr std::array<const char*, 36> iss::arch::traits<iss::arch::tgc_c>::reg_aliases;
constexpr std::array<const uint32_t, 42> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths; constexpr std::array<const uint32_t, 36> iss::arch::traits<iss::arch::tgc_c>::reg_bit_widths;
constexpr std::array<const uint32_t, 42> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets; constexpr std::array<const uint32_t, 36> iss::arch::traits<iss::arch::tgc_c>::reg_byte_offsets;
tgc_c::tgc_c() { tgc_c::tgc_c() = default;
reg.icount = 0;
}
tgc_c::~tgc_c() = default; tgc_c::~tgc_c() = default;
@ -57,8 +55,8 @@ void tgc_c::reset(uint64_t address) {
reg.PC=address; reg.PC=address;
reg.NEXT_PC=reg.PC; reg.NEXT_PC=reg.PC;
reg.PRIV=0x3; reg.PRIV=0x3;
reg.trap_state=0; trap_state=0;
reg.icount=0; icount=0;
} }
uint8_t *tgc_c::get_regs_base_ptr() { uint8_t *tgc_c::get_regs_base_ptr() {

3
src/plugin/pctrace.cpp
View File

@ -126,7 +126,8 @@ void iss::plugin::cov::callback(instr_info_t iinfo, const exec_info& einfo) {
auto delay = 0; auto delay = 0;
size_t id = iinfo.instr_id; size_t id = iinfo.instr_id;
auto entry = delays[id]; auto entry = delays[id];
auto call = (id==2 || id==3) && bit_sub<7,5>(instr_if->get_instr_word())!=0; auto instr = instr_if->get_instr_word();
auto call = (id==2 || id==3) && bit_sub<7,5>(instr)!=0;
bool taken = einfo.branch_taken; bool taken = einfo.branch_taken;
if (einfo.branch_taken) if (einfo.branch_taken)
delay = entry.taken; delay = entry.taken;

8
src/sysc/core_complex.cpp
View File

@ -105,7 +105,7 @@ public:
heart_state_t &get_state() { return this->state; } heart_state_t &get_state() { return this->state; }
void notify_phase(iss::arch_if::exec_phase p) override { void notify_phase(iss::arch_if::exec_phase p) override {
if (p == iss::arch_if::ISTART) owner->sync(this->reg.icount); if (p == iss::arch_if::ISTART) owner->sync(this->icount);
} }
sync_type needed_sync() const override { return PRE_SYNC; } sync_type needed_sync() const override { return PRE_SYNC; }
@ -115,7 +115,7 @@ public:
std::stringstream s; std::stringstream s;
s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0')
<< std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:"
<< this->reg.icount + this->cycle_offset << "]"; << this->icount + this->cycle_offset << "]";
SCCDEBUG(owner->name())<<"disass: " SCCDEBUG(owner->name())<<"disass: "
<< "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40) << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40)
<< std::setfill(' ') << std::left << instr << s.str(); << std::setfill(' ') << std::left << instr << s.str();
@ -175,7 +175,7 @@ public:
void wait_until(uint64_t flags) override { void wait_until(uint64_t flags) override {
SCCDEBUG(owner->name()) << "Sleeping until interrupt"; SCCDEBUG(owner->name()) << "Sleeping until interrupt";
while(this->reg.pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) { while(this->pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) {
sc_core::wait(wfi_evt); sc_core::wait(wfi_evt);
} }
PLAT::wait_until(flags); PLAT::wait_until(flags);
@ -204,7 +204,7 @@ public:
this->csr[arch::mip] &= ~mask; this->csr[arch::mip] &= ~mask;
this->check_interrupt(); this->check_interrupt();
if(value) if(value)
SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap; SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->pending_trap;
} }
private: private:

43
src/vm/interp/vm_tgc_c.cpp
View File

@ -115,7 +115,7 @@ protected:
inline void raise(uint16_t trap_id, uint16_t cause){ inline void raise(uint16_t trap_id, uint16_t cause){
auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id; auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val; this->core.trap_state = trap_val;
this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max(); this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
} }
@ -135,39 +135,39 @@ protected:
T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;} T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){ inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint8_t>(space, addr); auto ret = super::template read_mem<uint8_t>(space, addr);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
return ret; return ret;
} }
inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){ inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint16_t>(space, addr); auto ret = super::template read_mem<uint16_t>(space, addr);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
return ret; return ret;
} }
inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){ inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint32_t>(space, addr); auto ret = super::template read_mem<uint32_t>(space, addr);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
return ret; return ret;
} }
inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){ inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){
auto ret = super::template read_mem<uint64_t>(space, addr); auto ret = super::template read_mem<uint64_t>(space, addr);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
return ret; return ret;
} }
inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){ inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){
super::write_mem(space, addr, data); super::write_mem(space, addr, data);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
} }
inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){ inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){
super::write_mem(space, addr, data); super::write_mem(space, addr, data);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
} }
inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){ inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){
super::write_mem(space, addr, data); super::write_mem(space, addr, data);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
} }
inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){ inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){
super::write_mem(space, addr, data); super::write_mem(space, addr, data);
if(this->template get_reg<uint32_t>(traits::TRAP_STATE)) throw 0; if(this->core.trap_state) throw 0;
} }
template<unsigned W, typename U, typename S = typename std::make_signed<U>::type> template<unsigned W, typename U, typename S = typename std::make_signed<U>::type>
inline S sext(U from) { inline S sext(U from) {
@ -359,16 +359,15 @@ typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t
template <typename ARCH> template <typename ARCH>
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
auto pc=start; auto pc=start;
auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]); auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]); auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]); auto& trap_state = this->core.trap_state;
auto* icount = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]); auto& icount = this->core.icount;
auto* instret = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]); auto& cycle = this->core.cycle;
auto *const instruction = reinterpret_cast<code_word_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRUCTION]); auto& instret = this->core.instret;
auto& instr = this->core.instruction;
// we fetch at max 4 byte, alignment is 2 // we fetch at max 4 byte, alignment is 2
auto *const data = reinterpret_cast<uint8_t*>(instruction); auto *const data = reinterpret_cast<uint8_t*>(&instr);
auto& instr = *instruction;
while(!this->core.should_stop() && while(!this->core.should_stop() &&
!(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){ !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
@ -2409,16 +2408,16 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
process_spawn_blocks(); process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id)); if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
// trap check // trap check
if(*trap_state!=0){ if(trap_state!=0){
super::core.enter_trap(*trap_state, pc.val, instr); super::core.enter_trap(trap_state, pc.val, instr);
} else { } else {
(*icount)++; icount++;
(*instret)++; instret++;
} }
(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++; cycle++;
pc.val=*NEXT_PC; pc.val=*NEXT_PC;
this->core.reg.PC = this->core.reg.NEXT_PC; this->core.reg.PC = this->core.reg.NEXT_PC;
this->core.reg.trap_state = this->core.reg.pending_trap; this->core.trap_state = this->core.pending_trap;
} }
} }
return pc; return pc;