Added instruction enumeration and some cleanup

.gitignore

@@ -30,3 +30,4 @@ language.settings.xml
 /.gdbinit
 /*.out
 /dump.json
+/etc/

dbt-core

@@ -1 +1 @@
-Subproject commit 4bfcd8a10e81d610d46b329841ae3ba7cbc0627a
+Subproject commit 4eb39e8583e591b50c97051db7ac667c209459ab

riscv.sc/src/sc_main.cpp

@@ -70,7 +70,6 @@ int sc_main(int argc, char *argv[]) {
             ("elf,l", po::value<std::string>(), "ELF file to load")
             ("gdb-port,g", po::value<unsigned short>()->default_value(0), "enable gdb server and specify port to use")
             ("dump-ir", "dump the intermediate representation")
-            ("cycles", po::value<int64_t>()->default_value(-1), "number of cycles to run")
             ("quantum", po::value<unsigned>(), "SystemC quantum time in ns")
             ("reset,r", po::value<std::string>(), "reset address")
             ("trace,t", po::value<unsigned>()->default_value(0), "enable tracing, or combintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")

riscv/incl/iss/arch/riscv_hart_msu_vp.h

@@ -811,17 +811,18 @@ template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::write_csr(unsigned
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_cycle(unsigned addr, reg_t &val) {
+    auto cycle_val=this->cycles ? this->cycles : this->reg.icount;
     if (addr == mcycle) {
-        val = static_cast<reg_t>(this->reg.icount);
+        val = static_cast<reg_t>(cycle_val);
     } else if (addr == mcycleh) {
         if (sizeof(typename traits<BASE>::reg_t) != 4) return iss::Err;
-        val = static_cast<reg_t>((this->reg.icount) >> 32);
+        val = static_cast<reg_t>(cycle_val >> 32);
     }
     return iss::Ok;
 }
 
 template <typename BASE> iss::status riscv_hart_msu_vp<BASE>::read_time(unsigned addr, reg_t &val) {
-	uint64_t time_val=this->reg.icount>>12;
+	uint64_t time_val=(this->cycles?this->cycles:this->reg.icount) / (100000000/32768-1); //-> ~3052;
     if (addr == time) {
         val = static_cast<reg_t>(time_val);
     } else if (addr == timeh) {

riscv/incl/iss/arch/rv32imac.h

@@ -28,7 +28,7 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 // 
-// Created on: Fri Dec 15 14:41:57 CET 2017
+// Created on: Sat Dec 30 12:50:15 CET 2017
 //             *      rv32imac.h Author: <CoreDSL Generator>
 //
 ////////////////////////////////////////////////////////////////////////////////
@@ -159,45 +159,48 @@ struct rv32imac: public arch_if {
 
 protected:
     struct RV32IMAC_regs {
-        uint32_t X0;
+        uint32_t X0 = 0;
-        uint32_t X1;
+        uint32_t X1 = 0;
-        uint32_t X2;
+        uint32_t X2 = 0;
-        uint32_t X3;
+        uint32_t X3 = 0;
-        uint32_t X4;
+        uint32_t X4 = 0;
-        uint32_t X5;
+        uint32_t X5 = 0;
-        uint32_t X6;
+        uint32_t X6 = 0;
-        uint32_t X7;
+        uint32_t X7 = 0;
-        uint32_t X8;
+        uint32_t X8 = 0;
-        uint32_t X9;
+        uint32_t X9 = 0;
-        uint32_t X10;
+        uint32_t X10 = 0;
-        uint32_t X11;
+        uint32_t X11 = 0;
-        uint32_t X12;
+        uint32_t X12 = 0;
-        uint32_t X13;
+        uint32_t X13 = 0;
-        uint32_t X14;
+        uint32_t X14 = 0;
-        uint32_t X15;
+        uint32_t X15 = 0;
-        uint32_t X16;
+        uint32_t X16 = 0;
-        uint32_t X17;
+        uint32_t X17 = 0;
-        uint32_t X18;
+        uint32_t X18 = 0;
-        uint32_t X19;
+        uint32_t X19 = 0;
-        uint32_t X20;
+        uint32_t X20 = 0;
-        uint32_t X21;
+        uint32_t X21 = 0;
-        uint32_t X22;
+        uint32_t X22 = 0;
-        uint32_t X23;
+        uint32_t X23 = 0;
-        uint32_t X24;
+        uint32_t X24 = 0;
-        uint32_t X25;
+        uint32_t X25 = 0;
-        uint32_t X26;
+        uint32_t X26 = 0;
-        uint32_t X27;
+        uint32_t X27 = 0;
-        uint32_t X28;
+        uint32_t X28 = 0;
-        uint32_t X29;
+        uint32_t X29 = 0;
-        uint32_t X30;
+        uint32_t X30 = 0;
-        uint32_t X31;
+        uint32_t X31 = 0;
-        uint32_t PC;
+        uint32_t PC = 0;
-        uint32_t NEXT_PC;
+        uint32_t NEXT_PC = 0;
-        uint32_t trap_state, pending_trap, machine_state;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0;
-        uint64_t icount;
+        uint64_t icount = 0;
     } reg;
 
     address_type addr_mode[4];
+
+    uint64_t cycles = 0;
+
 };
 
 }

riscv/incl/iss/arch/rv64ia.h

@@ -28,7 +28,7 @@
 // ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
 // POSSIBILITY OF SUCH DAMAGE.
 // 
-// Created on: Fri Dec 15 14:41:58 CET 2017
+// Created on: Sat Dec 30 12:50:15 CET 2017
 //             *      rv64ia.h Author: <CoreDSL Generator>
 //
 ////////////////////////////////////////////////////////////////////////////////
@@ -159,45 +159,48 @@ struct rv64ia: public arch_if {
 
 protected:
     struct RV64IA_regs {
-        uint64_t X0;
+        uint64_t X0 = 0;
-        uint64_t X1;
+        uint64_t X1 = 0;
-        uint64_t X2;
+        uint64_t X2 = 0;
-        uint64_t X3;
+        uint64_t X3 = 0;
-        uint64_t X4;
+        uint64_t X4 = 0;
-        uint64_t X5;
+        uint64_t X5 = 0;
-        uint64_t X6;
+        uint64_t X6 = 0;
-        uint64_t X7;
+        uint64_t X7 = 0;
-        uint64_t X8;
+        uint64_t X8 = 0;
-        uint64_t X9;
+        uint64_t X9 = 0;
-        uint64_t X10;
+        uint64_t X10 = 0;
-        uint64_t X11;
+        uint64_t X11 = 0;
-        uint64_t X12;
+        uint64_t X12 = 0;
-        uint64_t X13;
+        uint64_t X13 = 0;
-        uint64_t X14;
+        uint64_t X14 = 0;
-        uint64_t X15;
+        uint64_t X15 = 0;
-        uint64_t X16;
+        uint64_t X16 = 0;
-        uint64_t X17;
+        uint64_t X17 = 0;
-        uint64_t X18;
+        uint64_t X18 = 0;
-        uint64_t X19;
+        uint64_t X19 = 0;
-        uint64_t X20;
+        uint64_t X20 = 0;
-        uint64_t X21;
+        uint64_t X21 = 0;
-        uint64_t X22;
+        uint64_t X22 = 0;
-        uint64_t X23;
+        uint64_t X23 = 0;
-        uint64_t X24;
+        uint64_t X24 = 0;
-        uint64_t X25;
+        uint64_t X25 = 0;
-        uint64_t X26;
+        uint64_t X26 = 0;
-        uint64_t X27;
+        uint64_t X27 = 0;
-        uint64_t X28;
+        uint64_t X28 = 0;
-        uint64_t X29;
+        uint64_t X29 = 0;
-        uint64_t X30;
+        uint64_t X30 = 0;
-        uint64_t X31;
+        uint64_t X31 = 0;
-        uint64_t PC;
+        uint64_t PC = 0;
-        uint64_t NEXT_PC;
+        uint64_t NEXT_PC = 0;
-        uint32_t trap_state, pending_trap, machine_state;
+        uint32_t trap_state = 0, pending_trap = 0, machine_state = 0;
-        uint64_t icount;
+        uint64_t icount = 0;
     } reg;
 
     address_type addr_mode[4];
+
+    uint64_t cycles = 0;
+    
 };
 
 }

riscv/src/internal/vm_riscv.in.cpp

@@ -186,17 +186,16 @@ private:
      ****************************************************************************/
     std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
                                                                           llvm::BasicBlock *bb) {
-        this->gen_sync(iss::PRE_SYNC);
+        this->gen_sync(iss::PRE_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
         this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
                                    get_reg_ptr(traits<ARCH>::PC), true);
         this->builder.CreateStore(
             this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
                                      this->gen_const(64U, 1)),
             get_reg_ptr(traits<ARCH>::ICOUNT), true);
-        if (this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
         pc = pc + ((instr & 3) == 3 ? 4 : 2);
         this->gen_raise_trap(0, 2);     // illegal instruction trap
-        this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
+        this->gen_sync(iss::POST_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
         this->gen_trap_check(this->leave_blk);
         return std::make_tuple(iss::vm::BRANCH, nullptr);
     }
@@ -227,8 +226,8 @@ std::tuple<vm::continuation_e, llvm::BasicBlock *>
 vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) {
     // we fetch at max 4 byte, alignment is 2
     code_word_t insn = 0;
-    iss::addr_t paddr;
     const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
+    phys_addr_t paddr(pc);
     try {
         uint8_t *const data = (uint8_t *)&insn;
         paddr = this->core.v2p(pc);

riscv/src/main.cpp

@@ -57,13 +57,11 @@ int main(int argc, char *argv[]) {
         ("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
         ("logfile,f", po::value<std::string>(), "Sets default log file.")
         ("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
-        ("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
         ("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
-        ("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")
+        ("instructions,i", po::value<int64_t>()->default_value(-1), "max. number of instructions to simulate")
-        ("dump-ir", "dump the intermediate representation")
-        ("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
-        ("time", po::value<int>(), "SystemC simulation time in ms")
         ("reset,r", po::value<std::string>(), "reset address")
+        ("dump-ir", "dump the intermediate representation")
+        ("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
         ("mem,m", po::value<std::string>(), "the memory input file")
         ("isa", po::value<std::string>()->default_value("rv32imac"), "isa to use for simulation");
     // clang-format on
@@ -137,7 +135,7 @@ int main(int argc, char *argv[]) {
             vm->reset();
         }
         int64_t cycles = -1;
-        cycles = clim["cycles"].as<int64_t>();
+        cycles = clim["instructions"].as<int64_t>();
         return vm->start(cycles, dump);
     } catch (std::exception &e) {
         LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"