DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

Added instruction enumeration and some cleanup

Browse Source
This commit is contained in:
Eyck Jentzsch
2017-12-31 11:27:51 +01:00
parent 873e4257f2
commit 9d40aa3aab
10 changed files with 653 additions and 651 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
riscv/src/internal/vm_riscv.in.cpp
View File

@ -186,17 +186,16 @@ private:
****************************************************************************/
std::tuple<vm::continuation_e, llvm::BasicBlock *> illegal_intruction(virt_addr_t &pc, code_word_t instr,
llvm::BasicBlock *bb) {
this->gen_sync(iss::PRE_SYNC);
this->gen_sync(iss::PRE_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
this->builder.CreateStore(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
get_reg_ptr(traits<ARCH>::PC), true);
this->builder.CreateStore(
this->builder.CreateAdd(this->builder.CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
this->gen_const(64U, 1)),
get_reg_ptr(traits<ARCH>::ICOUNT), true);
if (this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
pc = pc + ((instr & 3) == 3 ? 4 : 2);
this->gen_raise_trap(0, 2); // illegal instruction trap
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
this->gen_sync(iss::POST_SYNC, sizeof(instr_descr)/sizeof(InstructionDesriptor));
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
@ -227,8 +226,8 @@ std::tuple<vm::continuation_e, llvm::BasicBlock *>
vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt, llvm::BasicBlock *this_block) {
// we fetch at max 4 byte, alignment is 2
code_word_t insn = 0;
iss::addr_t paddr;
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
phys_addr_t paddr(pc);
try {
uint8_t *const data = (uint8_t *)&insn;
paddr = this->core.v2p(pc);

599
riscv/src/internal/vm_rv32imac.cpp
View File

File diff suppressed because it is too large Load Diff

523
riscv/src/internal/vm_rv64ia.cpp
View File

File diff suppressed because it is too large Load Diff

10
riscv/src/main.cpp
View File

@ -57,13 +57,11 @@ int main(int argc, char *argv[]) {
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
("logfile,f", po::value<std::string>(), "Sets default log file.")
("disass,d", po::value<std::string>()->implicit_value(""), "Enables disassembly")
("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
("gdb-port,g", po::value<unsigned>()->default_value(0), "enable gdb server and specify port to use")
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")
("dump-ir", "dump the intermediate representation")
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
("time", po::value<int>(), "SystemC simulation time in ms")
("instructions,i", po::value<int64_t>()->default_value(-1), "max. number of instructions to simulate")
("reset,r", po::value<std::string>(), "reset address")
("dump-ir", "dump the intermediate representation")
("elf", po::value<std::vector<std::string>>(), "ELF file(s) to load")
("mem,m", po::value<std::string>(), "the memory input file")
("isa", po::value<std::string>()->default_value("rv32imac"), "isa to use for simulation");
// clang-format on
@ -137,7 +135,7 @@ int main(int argc, char *argv[]) {
vm->reset();
}
int64_t cycles = -1;
cycles = clim["cycles"].as<int64_t>();
cycles = clim["instructions"].as<int64_t>();
return vm->start(cycles, dump);
} catch (std::exception &e) {
LOG(ERROR) << "Unhandled Exception reached the top of main: " << e.what() << ", application will now exit"