DBT-RISE/DBT-RISE-TGC
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Restructured project

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This commit is contained in:
Eyck Jentzsch 2017-09-21 20:29:23 +02:00
parent aa8c2138c6
commit 9a617dab57
55 changed files with 16145 additions and 166 deletions
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5
.cproject
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@ -151,11 +151,8 @@
</tool>
</toolChain>
</folderInfo>
<fileInfo id="cdt.managedbuild.config.gnu.exe.release.446935686.748801612" name="vm_riscv.in.cpp" rcbsApplicability="disable" resourcePath="riscv/src/internal/vm_riscv.in.cpp" toolsToInvoke="cdt.managedbuild.tool.gnu.cpp.compiler.exe.release.1265053613.1256835897">
<tool id="cdt.managedbuild.tool.gnu.cpp.compiler.exe.release.1265053613.1256835897" name="GCC C++ Compiler" superClass="cdt.managedbuild.tool.gnu.cpp.compiler.exe.release.1265053613"/>
</fileInfo>
<sourceEntries>
<entry excluding="riscv/src/internal/vm_riscv.in.cpp|riscv/src-gen|blink.S" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
<entry excluding="riscv/src-gen|blink.S|riscv/src/internal/vm_riscv.in.cpp" flags="VALUE_WORKSPACE_PATH|RESOLVED" kind="sourcePath" name=""/>
</sourceEntries>
</configuration>
</storageModule>

1
CMakeLists.txt
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@ -31,3 +31,4 @@ add_subdirectory(external)
add_subdirectory(dbt-core)
add_subdirectory(sc-components)
add_subdirectory(riscv)
add_subdirectory(riscv.sc)

2
dbt-core

@ -1 +1 @@
Subproject commit df6f6eb713c3c0a2dc10ba29e80d586a9f66a25f
Subproject commit 1091afcc3045c1bea5508a6be785eed757632452

6
external/CMakeLists.txt vendored
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@ -8,18 +8,16 @@ project("external")
include(Common)
include_directories( ${PROJECT_SOURCE_DIR}/external/libGIS ${PROJECT_SOURCE_DIR}/external/easyloggingpp/src )
include_directories( ${PROJECT_SOURCE_DIR}/external/libGIS )
FILE(GLOB ElfioHeaders elfio *.hpp)
FILE(GLOB GISHeaders libGis *.h)
FILE(GLOB LogHeaders easyloggingpp/src *.h)
set(LIB_HEADERS ${ElfioHeaders} ${GISHeaders} ${LogHeaders})
set(LIB_HEADERS ${ElfioHeaders} ${GISHeaders})
set(LIB_SOURCES
libGIS/atmel_generic.c
libGIS/ihex.c
libGIS/srecord.c
easyloggingpp/src/easylogging++.cc
)
# Define two variables in order not to repeat ourselves.

95
riscv.sc/CMakeLists.txt Normal file
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@ -0,0 +1,95 @@
cmake_minimum_required(VERSION 2.8)
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/../cmake) # main (top) cmake dir
set(CMAKE_MODULE_PATH ${CMAKE_MODULE_PATH} ${CMAKE_CURRENT_SOURCE_DIR}/cmake) # project specific cmake dir
set(CMAKE_CXX_STANDARD 14) # tODO move up to a general cmake config for all sub projects ?
# CMake useful variables
set(CMAKE_RUNTIME_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/bin")
set(CMAKE_ARCHIVE_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib")
set(CMAKE_LIBRARY_OUTPUT_DIRECTORY "${CMAKE_BINARY_DIR}/lib")
# Set the name of your project here
project("riscv.sc")
# Set the version number of your project here (format is MAJOR.MINOR.PATCHLEVEL - e.g. 1.0.0)
set(VERSION_MAJOR "0")
set(VERSION_MINOR "0")
set(VERSION_PATCH "1")
set(VERSION ${VERSION_MAJOR}.${VERSION_MINOR}.${VERSION_PATCH})
include(Common)
## Git (and its revision)
find_package(Git QUIET) # if we don't find git or FindGit.cmake is not on the system we ignore it.
## The Git module will trigger a reconfiguration for each pull that will bring a new revision on the local repository
set (VCS_REVISION "-1")
if(GIT_FOUND)
include(GetGitRevisionDescription)
get_git_head_revision(GIT_REFSPEC GIT_SHA1)
message(STATUS "GIT branch ${GIT_REFSPEC}")
message(STATUS "GIT revision ${GIT_SHA1}")
set (VCS_REVISION ${GIT_SHA1})
endif()
# This line finds the boost lib and headers.
set(Boost_NO_BOOST_CMAKE ON) # Don't do a find_package in config mode before searching for a regular boost install.
find_package(Boost COMPONENTS program_options system thread REQUIRED)
find_package(LLVM REQUIRED CONFIG)
message(STATUS "Found LLVM ${LLVM_PACKAGE_VERSION}")
message(STATUS "Using LLVMConfig.cmake in: ${LLVM_DIR}")
llvm_map_components_to_libnames(llvm_libs support core mcjit x86codegen x86asmparser)
find_package(SystemC)
if(SystemC_FOUND)
add_definitions(-DWITH_SYSTEMC)
include_directories(${SystemC_INCLUDE_DIRS})
link_directories(${SystemC_LIBRARY_DIRS})
else(SystemC_FOUND)
message( FATAL_ERROR "SystemC library not found." )
endif(SystemC_FOUND)
if(SCV_FOUND)
add_definitions(-DWITH_SCV)
link_directories(${SCV_LIBRARY_DIRS})
endif(SCV_FOUND)
# This sets the include directory for the reference project. This is the -I flag in gcc.
include_directories(
${PROJECT_SOURCE_DIR}/incl
${LLVM_INCLUDE_DIRS}
)
add_dependent_subproject(dbt-core)
add_dependent_subproject(sc-components)
add_dependent_header(util)
include_directories(
${PROJECT_SOURCE_DIR}/incl
${PROJECT_SOURCE_DIR}/../external/elfio
${PROJECT_SOURCE_DIR}/../external/libGIS
${PROJECT_SOURCE_DIR}/../riscv
${Boost_INCLUDE_DIRS}
)
# Mac needed variables (adapt for your needs - http://www.cmake.org/Wiki/CMake_RPATH_handling#Mac_OS_X_and_the_RPATH)
set(CMAKE_MACOSX_RPATH ON)
set(CMAKE_SKIP_BUILD_RPATH FALSE)
set(CMAKE_BUILD_WITH_INSTALL_RPATH FALSE)
set(CMAKE_INSTALL_RPATH "${CMAKE_INSTALL_PREFIX}/lib")
set(CMAKE_INSTALL_RPATH_USE_LINK_PATH TRUE)
add_subdirectory(src)
#
# SYSTEM PACKAGING (RPM, TGZ, ...)
# _____________________________________________________________________________
#include(CPackConfig)
#
# CMAKE PACKAGING (for other CMake projects to use this one easily)
# _____________________________________________________________________________
#include(PackageConfigurator)

0
riscv/fe310.rdl → riscv.sc/gen_input/fe310.rdl
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0
riscv/gpio.rdl → riscv.sc/gen_input/gpio.rdl
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4
riscv/plic.rdl → riscv.sc/gen_input/plic.rdl
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@ -26,12 +26,12 @@ regfile plic_regs {
field {
name = "threshold";
} \threshold[2:0];
} \threshold @0x0C200000;
} \threshold @0x200000;
reg {
name="claim/complete";
desc="interrupt handling completed";
field {
name = "interrupt_claimed";
} interrupt_claimed[31:0];
} claim_complete @0x0C200004;
} claim_complete @0x200004;
};

174
riscv.sc/gen_input/spi.rdl Normal file
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@ -0,0 +1,174 @@
regfile spi_regs {
lsb0;
reg {
name="sckdiv";
desc="Serial clock divisor";
field {
name ="div";
} div[12];
} sckdiv @0x000;
reg {
name="sckmode";
desc="Serial clock mode";
field {
name="pha";
} pha[1];
field {
name="pol";
} pol[1];
} sckmode @0x004;
reg {
name="csid";
desc="Chip select ID";
field {
name="csid";
} csid[32];
} csid @0x010;
reg {
name="csdef";
desc="Chip select default";
field {
name="csdef";
} csdef[32];
} csdef @0x014;
reg {
name="csmode";
desc="Chip select mode";
field {
name="mode";
} mode[2];
} csmode @0x018;
reg {
name="delay0";
desc="Delay control 0";
field {
name="cssck";
} cssck[7:0];
field {
name ="sckcs";
} sckcs[23:16];
} delay0 @0x028;
reg {
name="delay1";
desc="Delay control 1";
field {
name="intercs";
}intercs[15:0];
field {
name="interxfr";
} interxfr[23:16];
} delay1 @0x02C;
reg {
name="fmt";
desc="Frame format";
field{
name ="proto";
}proto[2];
field {
name="endian";
} endian[1];
field {
name="dir";
} dir[1];
field {
name="len";
} len[19:16];
} fmt @0x040;
reg {
name="txdata";
desc="Tx FIFO data";
field {
name="data";
} data[8];
field {
name="full";
} full[31:31];
} txdata @0x048;
reg {
name="rxdata";
desc="Rx FIFO data";
field{
name="data";
} data[8];
field{
name="empty";
} empty[31:31];
} rxdata @0x04C;
reg {
name="txmark";
desc="Tx FIFO watermark";
field {
name="txmark";
} txmark[3];
} txmark @0x050;
reg {
name="rxmark";
desc="Rx FIFO watermark";
field {
name="rxmark";
} rxmark[3];
} rxmark @0x054;
reg {
name="fctrl";
desc="SPI flash interface control";
field {
name="en";
} en[1];
} fctrl @0x060;
reg {
name="ffmt";
desc="SPI flash instruction format";
field {
name="cmd_en";
reset=0x1;
} cmd_en[1];
field {
name="addr_len";
reset=0x3;
} addr_len[2];
field {
name="pad_cnt";
reset=0x0;
} pad_cnt[4];
field {
name="cmd_proto";
reset=0x0;
} cmd_proto[2];
field {
name="addr_proto";
reset=0x0;
} addr_proto[2];
field {
name="data_proto";
reset=0x0;
} data_proto[2];
field {
name="cmd_code";
reset=0x3;
} cmd_code[23:16];
field {
name="pad_code";
reset=0x0;
} pad_code[8];
} ffmt @0x064;
reg {
name="ie";
desc="SPI interrupt enable";
field{
name="txwm";
} txwm[1];
field{
name="rxwm";
} rxwm[1];
} ie @0x070;
reg {
name="ip";
desc="SPI interrupt pending";
field{
name="txwm";
} txwm[1];
field{
name="rxwm";
} rxwm[1];
} ip @0x074;
};

81
riscv.sc/gen_input/uart.rdl Normal file
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@ -0,0 +1,81 @@
regfile uart_regs {
lsb0;
reg {
name="txdata";
desc="Transmit data register";
field {
name ="data";
} data[7:0];
field {
name ="full";
} full[31:31];
} txdata @0x00;
reg {
name="rxdata";
desc="Receive data register";
field {
name ="data";
} data[7:0];
field {
name ="empty";
} empty[31:31];
}rxdata @0x04;
reg {
name="txctrl";
desc="Transmit control register";
field {
name ="txen";
} txen[1];
field {
name ="nstop";
} nstop[1];
field {
name ="reserved";
} reserved[14];
field {
name ="txcnt";
} txcnt[3];
}txctrl @0x08;
reg {
name="rxctrl";
desc="Receive control register";
field {
name ="rxen";
} rxen[1];
field {
name ="reserved";
} reserved[15];
field {
name ="rxcnt";
} rxcnt[3];
}rxctrl @0x0C;
reg {
name="ie";
desc="UART interrupt enable";
field{
name ="txwm";
} txwm[1];
field{
name ="rxwm";
} rxwm[1];
}ie @0x10;
reg {
name="ip";
desc="UART Interrupt pending";
field{
name ="txwm";
} txwm[1];
field{
name ="rxwm";
} rxwm[1];
} ip @0x14;
reg {
name="div";
desc="Baud rate divisor";
field{
name ="div";
} div[16];
} div @0x18;
};

171
riscv.sc/incl/cli_options.h Normal file
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@ -0,0 +1,171 @@
/*******************************************************************************
* Copyright (C) 2017, MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* Contributors:
* eyck@minres.com - initial API and implementation
******************************************************************************/
#ifndef _CLI_OPTIONS_H_
#define _CLI_OPTIONS_H_
#include <boost/program_options.hpp>
#include <util/logging.h>
#include <iostream>
#include <cstdio>
namespace {
const size_t ERROR_IN_COMMAND_LINE = 1;
const size_t SUCCESS = 0;
const size_t ERROR_UNHANDLED_EXCEPTION = 2;
inline void enable_log_level(int level){
switch(level){
case 0:
logging::Logger::reporting_level()= logging::FATAL;
/* no break */
case 1:
logging::Logger::reporting_level()= logging::ERROR;
/* no break */
case 2:
logging::Logger::reporting_level()= logging::WARNING;
/* no break */
case 3:
logging::Logger::reporting_level()= logging::INFO;
/* no break */
case 4:
logging::Logger::reporting_level()= logging::DEBUG;
/* no break */
case 5:
logging::Logger::reporting_level()= logging::TRACE;
/* no break */
}
}
inline void configure_default_logger(boost::program_options::variables_map& vm){
// el::Configurations defaultConf;
// defaultConf.setToDefault();
// defaultConf.set(el::Level::Error, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Warning, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Info, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Debug, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
// defaultConf.set(el::Level::Trace, el::ConfigurationType::Format, "%datetime{%H:%m:%s.%g} %level %msg");
if(vm.count("verbose"))
enable_log_level(vm["verbose"].as<int>());
if(vm.count("log-file"))
logging::Output2FILE::stream() = fopen(vm["log-file"].as<std::string>().c_str(), "w");
// default logger uses default configurations
// el::Loggers::reconfigureLogger("default", defaultConf);
}
inline void configure_debugger_logger() {
// configure the connection logger
// el::Logger* gdbServerLogger = el::Loggers::getLogger("connection");
// el::Configurations gdbServerConf;
// gdbServerConf.setToDefault();
// gdbServerConf.set(el::Level::Error, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Warning, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Info, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Debug, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// gdbServerConf.set(el::Level::Trace, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} %level [%logger] %msg");
// enable_log_level(gdbServerConf, 5);
// gdbServerLogger->configure(gdbServerConf);
}
inline void configure_disass_logger(boost::program_options::variables_map& vm) {
// el::Logger* disassLogger = el::Loggers::getLogger("disass");
// el::Configurations disassConf;
// if(vm.count("disass")){
// auto file_name=vm["disass"].as<std::string>();
// disassConf.setToDefault();
// if (file_name.length() > 0) {
// disassConf.set(el::Level::Global, el::ConfigurationType::ToFile,
// std::string("true"));
// disassConf.set(el::Level::Global,
// el::ConfigurationType::ToStandardOutput, std::string("false"));
// disassConf.set(el::Level::Global, el::ConfigurationType::Format,
// std::string("%msg"));
// disassConf.set(el::Level::Global, el::ConfigurationType::Filename,
// file_name);
// std::ofstream str(file_name); // just to clear the file
// } else {
// disassConf.set(el::Level::Global, el::ConfigurationType::Format,
// "%datetime{%H:%m:%s.%g} [%logger] %msg");
// }
// } else {
// enable_log_level(disassConf, 0);
// }
// disassLogger->configure(disassConf);
}
} // namespace
inline int parse_cli_options(boost::program_options::variables_map& vm, int argc, char *argv[]){
namespace po = boost::program_options;
po::options_description desc("Options");
desc.add_options()
("help,h", "Print help message")
("verbose,v", po::value<int>()->implicit_value(0), "Sets logging verbosity")
("vmodule", po::value<std::string>(),"Defines the module(s) to be logged")
("logging-flags", po::value<int>(),"Sets logging flag(s).")
("log-file", po::value<std::string>(),"Sets default log file.")
("disass,d", po::value<std::string>()->implicit_value(""),"Enables disassembly")
("elf,l", po::value< std::vector<std::string> >(), "ELF file(s) to load")
("gdb-port,g", po::value<unsigned>(), "enable gdb server and specify port to use")
("input,i", po::value<std::string>(), "the elf file to load (instead of hex files)")
("dump-ir", "dump the intermediate representation")
("cycles,c", po::value<int64_t>()->default_value(-1), "number of cycles to run")
("systemc,s", "Run as SystemC simulation")
("time", po::value<int>(), "SystemC siimulation time in ms")
("reset,r", po::value<std::string>(), "reset address")
("trace", po::value<uint8_t>(), "enable tracing, or cmbintation of 1=signals and 2=TX text, 4=TX compressed text, 6=TX in SQLite")\
("mem,m", po::value<std::string>(), "the memory input file")
("rv64", "run RV64");
try {
po::store(po::parse_command_line(argc, argv, desc), vm); // can throw
// --help option
if ( vm.count("help") ){
std::cout << "DBT-RISE-RiscV" << std::endl << desc << std::endl;
return SUCCESS;
}
po::notify(vm); // throws on error, so do after help in case
} catch(po::error& e){
// there are problems
std::cerr << "ERROR: " << e.what() << std::endl << std::endl;
std::cerr << desc << std::endl;
return ERROR_IN_COMMAND_LINE;
}
return SUCCESS;
}
#endif /* _CLI_OPTIONS_H_ */

1249
riscv.sc/incl/iss/arch/riscv_hart_msu_vp.h Normal file
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200
riscv.sc/incl/iss/arch/rv32imac.h Normal file
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@ -0,0 +1,200 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv32imac.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _RV32IMAC_H_
#define _RV32IMAC_H_
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss {
namespace arch {
struct rv32imac;
template<>
struct traits<rv32imac> {
enum constants {XLEN=32,XLEN2=64,XLEN_BIT_MASK=31,PCLEN=32,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=1075056897,PGSIZE=4096,PGMASK=4095};
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
ICOUNT
};
typedef uint32_t reg_t;
typedef uint32_t addr_t;
typedef uint32_t code_word_t; //TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV32IMAC_reg_size[] = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,64};
return RV32IMAC_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV32IMAC_reg_byte_offset[] = {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,140,144,152,160};
return RV32IMAC_reg_byte_offset[r];
}
enum sreg_flag_e {FLAGS};
enum mem_type_e {MEM,CSR,FENCE,RES};
};
struct rv32imac: public arch_if {
using virt_addr_t = typename traits<rv32imac>::virt_addr_t;
using phys_addr_t = typename traits<rv32imac>::phys_addr_t;
using reg_t = typename traits<rv32imac>::reg_t;
using addr_t = typename traits<rv32imac>::addr_t;
rv32imac();
~rv32imac();
virtual void reset(uint64_t address=0) override;
virtual uint8_t* get_regs_base_ptr() override;
/// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
virtual bool get_flag(int flag) override {return false;}
virtual void set_flag(int, bool value) override {};
/// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
virtual void notify_phase(exec_phase phase){
if(phase==ISTART){
++reg.icount;
reg.PC=reg.NEXT_PC;
reg.trap_state=reg.pending_trap;
}
}
uint64_t get_icount() { return reg.icount;}
virtual phys_addr_t v2p(const iss::addr_t& pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
protected:
struct RV32IMAC_regs {
uint32_t X0;
uint32_t X1;
uint32_t X2;
uint32_t X3;
uint32_t X4;
uint32_t X5;
uint32_t X6;
uint32_t X7;
uint32_t X8;
uint32_t X9;
uint32_t X10;
uint32_t X11;
uint32_t X12;
uint32_t X13;
uint32_t X14;
uint32_t X15;
uint32_t X16;
uint32_t X17;
uint32_t X18;
uint32_t X19;
uint32_t X20;
uint32_t X21;
uint32_t X22;
uint32_t X23;
uint32_t X24;
uint32_t X25;
uint32_t X26;
uint32_t X27;
uint32_t X28;
uint32_t X29;
uint32_t X30;
uint32_t X31;
uint32_t PC;
uint32_t NEXT_PC;
uint32_t trap_state, pending_trap, machine_state;
uint64_t icount;
} reg;
};
}
}
#endif /* _RV32IMAC_H_ */

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////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv64ia.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _RV64IA_H_
#define _RV64IA_H_
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss {
namespace arch {
struct rv64ia;
template<>
struct traits<rv64ia> {
enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147750144,PGSIZE=4096,PGMASK=4095};
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
ICOUNT
};
typedef uint64_t reg_t;
typedef uint64_t addr_t;
typedef uint64_t code_word_t; //TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64};
return RV64IA_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296};
return RV64IA_reg_byte_offset[r];
}
enum sreg_flag_e {FLAGS};
enum mem_type_e {MEM,CSR,FENCE,RES};
};
struct rv64ia: public arch_if {
using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
using reg_t = typename traits<rv64ia>::reg_t;
using addr_t = typename traits<rv64ia>::addr_t;
rv64ia();
~rv64ia();
virtual void reset(uint64_t address=0) override;
virtual uint8_t* get_regs_base_ptr() override;
/// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
virtual bool get_flag(int flag) override {return false;}
virtual void set_flag(int, bool value) override {};
/// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
virtual void notify_phase(exec_phase phase){
if(phase==ISTART){
++reg.icount;
reg.PC=reg.NEXT_PC;
reg.trap_state=reg.pending_trap;
}
}
uint64_t get_icount() { return reg.icount;}
virtual phys_addr_t v2p(const iss::addr_t& pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
protected:
struct RV64IA_regs {
uint64_t X0;
uint64_t X1;
uint64_t X2;
uint64_t X3;
uint64_t X4;
uint64_t X5;
uint64_t X6;
uint64_t X7;
uint64_t X8;
uint64_t X9;
uint64_t X10;
uint64_t X11;
uint64_t X12;
uint64_t X13;
uint64_t X14;
uint64_t X15;
uint64_t X16;
uint64_t X17;
uint64_t X18;
uint64_t X19;
uint64_t X20;
uint64_t X21;
uint64_t X22;
uint64_t X23;
uint64_t X24;
uint64_t X25;
uint64_t X26;
uint64_t X27;
uint64_t X28;
uint64_t X29;
uint64_t X30;
uint64_t X31;
uint64_t PC;
uint64_t NEXT_PC;
uint32_t trap_state, pending_trap, machine_state;
uint64_t icount;
} reg;
};
}
}
#endif /* _RV64IA_H_ */

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# library files
FILE(GLOB RiscVSCHeaders *.h)
set(LIB_HEADERS ${RiscVSCHeaders} )
set(LIB_SOURCES
sysc/core_complex.cpp
sysc/gpio.cpp
sysc/plic.cpp
sysc/platform.cpp
sysc/spi.cpp
sysc/uart.cpp
)
set(APP_HEADERS )
set(APP_SOURCES sc_main.cpp
)
# Define two variables in order not to repeat ourselves.
set(LIBRARY_NAME risc-v.sc)
# Define the library
add_library(${LIBRARY_NAME} ${LIB_SOURCES})
set_target_properties(${LIBRARY_NAME} PROPERTIES
VERSION ${VERSION} # ${VERSION} was defined in the main CMakeLists.
FRAMEWORK FALSE
PUBLIC_HEADER "${LIB_HEADERS}" # specify the public headers
)
# This is a make target, so you can do a "make riscv-sc"
set(APPLICATION_NAME riscv.sc)
add_executable(${APPLICATION_NAME} ${APP_SOURCES})
# Links the target exe against the libraries
target_link_libraries(${APPLICATION_NAME} ${LIBRARY_NAME})
target_link_libraries(${APPLICATION_NAME} dbt-core)
target_link_libraries(${APPLICATION_NAME} sc-components)
target_link_libraries(${APPLICATION_NAME} external)
target_link_libraries(${APPLICATION_NAME} risc-v)
target_link_libraries(${APPLICATION_NAME} ${llvm_libs})
target_link_libraries(${APPLICATION_NAME} ${SystemC_LIBRARIES} )
if(SCV_FOUND)
target_link_libraries (${APPLICATION_NAME} ${SCV_LIBRARIES})
endif()
target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} )
# Says how and where to install software
# Targets:
# * <prefix>/lib/<libraries>
# * header location after install: <prefix>/include/<project>/*.h
# * headers can be included by C++ code `#<project>/Bar.hpp>`
install(TARGETS ${LIBRARY_NAME} ${APPLICATION_NAME}
EXPORT ${PROJECT_NAME}Targets # for downstream dependencies
ARCHIVE DESTINATION lib COMPONENT libs # static lib
RUNTIME DESTINATION bin COMPONENT libs # binaries
LIBRARY DESTINATION lib COMPONENT libs # shared lib
FRAMEWORK DESTINATION bin COMPONENT libs # for mac
PUBLIC_HEADER DESTINATION incl/${PROJECT_NAME} COMPONENT devel # headers for mac (note the different component -> different package)
INCLUDES DESTINATION incl # headers
)

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////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Contributors:
// eyck@minres.com - initial API and implementation
//
//
////////////////////////////////////////////////////////////////////////////////
#include <iss/iss.h>
#include <iss/debugger/gdb_session.h>
#include <util/logging.h>
#include <memory>
#include <cstring>
#include "iss/vm_base.h"
#include "iss/arch/CORE_DEF_NAME.h"
#include "iss/debugger/server.h"
#include <boost/format.hpp>
#include "iss/arch/riscv_hart_msu_vp.h"
namespace iss {
namespace CORE_DEF_NAME {
using namespace iss::arch;
using namespace llvm;
using namespace iss::debugger;
template<typename ARCH>
struct vm_impl;
template<typename ARCH>
struct target_adapter: public target_adapter_base {
target_adapter(server_if* srv, vm_impl<ARCH>* vm)
: target_adapter_base(srv)
, vm(vm)
{
}
/*============== Thread Control ===============================*/
/* Set generic thread */
status set_gen_thread(rp_thread_ref& thread) override;
/* Set control thread */
status set_ctrl_thread(rp_thread_ref& thread) override;
/* Get thread status */
status is_thread_alive(rp_thread_ref& thread, bool& alive) override;
/*============= Register Access ================================*/
/* Read all registers. buf is 4-byte aligned and it is in
target byte order. If register is not available
corresponding bytes in avail_buf are 0, otherwise
avail buf is 1 */
status read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) override;
/* Write all registers. buf is 4-byte aligned and it is in target
byte order */
status write_registers(const std::vector<uint8_t>& data) override;
/* Read one register. buf is 4-byte aligned and it is in
target byte order. If register is not available
corresponding bytes in avail_buf are 0, otherwise
avail buf is 1 */
status read_single_register(unsigned int reg_no, std::vector<uint8_t>& buf, std::vector<uint8_t>& avail_buf) override;
/* Write one register. buf is 4-byte aligned and it is in target byte
order */
status write_single_register(unsigned int reg_no, const std::vector<uint8_t>& buf) override;
/*=================== Memory Access =====================*/
/* Read memory, buf is 4-bytes aligned and it is in target
byte order */
status read_mem(uint64_t addr, std::vector<uint8_t>& buf) override;
/* Write memory, buf is 4-bytes aligned and it is in target
byte order */
status write_mem(uint64_t addr, const std::vector<uint8_t>& buf) override;
status process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) override;
status thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num, size_t& num, bool& done) override;
status current_thread_query(rp_thread_ref& thread) override;
status offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) override;
status crc_query(uint64_t addr, size_t len, uint32_t& val) override;
status raw_query(std::string in_buf, std::string& out_buf) override;
status threadinfo_query(int first, std::string& out_buf) override;
status threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) override;
status packetsize_query(std::string& out_buf) override;
status add_break(int type, uint64_t addr, unsigned int length) override;
status remove_break(int type, uint64_t addr, unsigned int length) override;
status resume_from_addr(bool step, int sig, uint64_t addr) override;
protected:
static inline constexpr addr_t map_addr(const addr_t& i){
return i;
}
vm_impl<ARCH>* vm;
rp_thread_ref thread_idx;
};
template<typename ARCH>
struct vm_impl: public vm::vm_base<ARCH> {
using super = typename vm::vm_base<ARCH>;
using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
using addr_t = typename super::addr_t ;
vm_impl();
vm_impl(ARCH& core, bool dump=false);
void enableDebug(bool enable) {
super::sync_exec=super::ALL_SYNC;
}
target_adapter_if* accquire_target_adapter(server_if* srv){
debugger_if::dbg_enabled=true;
if(vm::vm_base<ARCH>::tgt_adapter==nullptr)
vm::vm_base<ARCH>::tgt_adapter=new target_adapter<ARCH>(srv, this);
return vm::vm_base<ARCH>::tgt_adapter;
}
protected:
template<typename T> inline
llvm::ConstantInt* size(T type){
return llvm::ConstantInt::get(getContext(), llvm::APInt(32, type->getType()->getScalarSizeInBits()));
}
inline llvm::Value * gen_choose(llvm::Value * cond, llvm::Value * trueVal, llvm::Value * falseVal, unsigned size) const {
return this->gen_cond_assign(cond, this->gen_ext(trueVal, size), this->gen_ext(falseVal, size));
}
std::tuple<vm::continuation_e, llvm::BasicBlock*> gen_single_inst_behavior(virt_addr_t&, unsigned int&, llvm::BasicBlock*) override;
void gen_leave_behavior(llvm::BasicBlock* leave_blk) override;
void gen_raise_trap(uint16_t trap_id, uint16_t cause);
void gen_leave_trap(unsigned lvl);
void gen_wait(unsigned type);
void gen_trap_behavior(llvm::BasicBlock*) override;
void gen_trap_check(llvm::BasicBlock* bb);
inline
void gen_set_pc(virt_addr_t pc, unsigned reg_num){
llvm::Value* next_pc_v = this->builder->CreateSExtOrTrunc(this->gen_const(traits<ARCH>::XLEN, pc.val), this->get_type(traits<ARCH>::XLEN));
this->builder->CreateStore(next_pc_v, get_reg_ptr(reg_num), true);
}
inline
llvm::Value* get_reg_ptr(unsigned i){
void* ptr = this->core.get_regs_base_ptr()+traits<ARCH>::reg_byte_offset(i);
llvm::PointerType* ptrType=nullptr;
switch (traits<ARCH>::reg_bit_width(i)>>3) {
case 8:
ptrType=llvm::Type::getInt64PtrTy(this->mod->getContext());
break;
case 4:
ptrType=llvm::Type::getInt32PtrTy(this->mod->getContext());
break;
case 2:
ptrType=llvm::Type::getInt16PtrTy(this->mod->getContext());
break;
case 1:
ptrType=llvm::Type::getInt8PtrTy(this->mod->getContext());
break;
default:
throw std::runtime_error("unsupported access with");
break;
}
return llvm::ConstantExpr::getIntToPtr(
llvm::ConstantInt::get(this->mod->getContext(), llvm::APInt(
8/*bits*/ * sizeof(uint8_t*),
reinterpret_cast<uint64_t>(ptr)
)),
ptrType);
}
inline
llvm::Value* gen_reg_load(unsigned i, unsigned level=0){
// if(level){
return this->builder->CreateLoad(get_reg_ptr(i), false);
// } else {
// if(!this->loaded_regs[i])
// this->loaded_regs[i]=this->builder->CreateLoad(get_reg_ptr(i), false);
// return this->loaded_regs[i];
// }
}
inline
void gen_set_pc(virt_addr_t pc){
llvm::Value* pc_l = this->builder->CreateSExt(this->gen_const(traits<ARCH>::caddr_bit_width, (unsigned)pc), this->get_type(traits<ARCH>::caddr_bit_width));
super::gen_set_reg(traits<ARCH>::PC, pc_l);
}
// some compile time constants
enum {MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111};
enum {EXTR_MASK16 = MASK16>>2, EXTR_MASK32 = MASK32>>2};
enum {LUT_SIZE = 1<< bit_count(EXTR_MASK32), LUT_SIZE_C = 1<<bit_count(EXTR_MASK16)};
using this_class = vm_impl<ARCH>;
using compile_func = std::tuple<vm::continuation_e, llvm::BasicBlock*> (this_class::*)(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb);
compile_func lut[LUT_SIZE];
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
std::array<compile_func, LUT_SIZE> lut_11;
compile_func* qlut[4];// = {lut_00, lut_01, lut_10, lut_11};
const uint32_t lutmasks[4]={EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32};
void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[], compile_func f){
if(pos<0){
lut[idx]=f;
} else {
auto bitmask = 1UL<<pos;
if((mask & bitmask)==0){
expand_bit_mask(pos-1, mask, value, valid, idx, lut, f);
} else {
if((valid & bitmask) == 0) {
expand_bit_mask(pos-1, mask, value, valid, (idx<<1), lut, f);
expand_bit_mask(pos-1, mask, value, valid, (idx<<1)+1, lut, f);
} else {
auto new_val = idx<<1;
if((value&bitmask)!=0)
new_val++;
expand_bit_mask(pos-1, mask, value, valid, new_val, lut, f);
}
}
}
}
inline uint32_t extract_fields(uint32_t val){
return extract_fields(29, val>>2, lutmasks[val&0x3], 0);
}
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val){
if(pos>=0) {
auto bitmask = 1UL<<pos;
if((mask & bitmask)==0){
lut_val = extract_fields(pos-1, val, mask, lut_val);
} else {
auto new_val = lut_val<<1;
if((val&bitmask)!=0)
new_val++;
lut_val = extract_fields(pos-1, val, mask, new_val);
}
}
return lut_val;
}
private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct InstructionDesriptor {
size_t length;
uint32_t value;
uint32_t mask;
compile_func op;
};
/* «start generated code» */
InstructionDesriptor instr_descr[0] = {};
/* «end generated code» */
/****************************************************************************
* end opcode definitions
****************************************************************************/
std::tuple<vm::continuation_e, llvm::BasicBlock*> illegal_intruction(virt_addr_t& pc, code_word_t instr, llvm::BasicBlock* bb){
//this->gen_sync(iss::PRE_SYNC);
this->builder->CreateStore(
this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), true),
get_reg_ptr(traits<ARCH>::PC), true);
this->builder->CreateStore(
this->builder->CreateAdd(
this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::ICOUNT), true),
this->gen_const(64U, 1)),
get_reg_ptr(traits<ARCH>::ICOUNT), true);
if(this->debugging_enabled()) this->gen_sync(iss::PRE_SYNC);
pc=pc+((instr&3) == 3?4:2);
this->gen_raise_trap(0, 2); // illegal instruction trap
this->gen_sync(iss::POST_SYNC); /* call post-sync if needed */
this->gen_trap_check(this->leave_blk);
return std::make_tuple(iss::vm::BRANCH, nullptr);
}
};
template<typename CODE_WORD>
void debug_fn(CODE_WORD insn){
volatile CODE_WORD x=insn;
insn=2*x;
}
template<typename ARCH>
vm_impl<ARCH>::vm_impl(){
this(new ARCH());
}
template<typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH& core, bool dump) : vm::vm_base<ARCH>(core, dump) {
qlut[0] = lut_00.data();
qlut[1] = lut_01.data();
qlut[2] = lut_10.data();
qlut[3] = lut_11.data();
for(auto instr: instr_descr){
auto quantrant = instr.value&0x3;
expand_bit_mask(29, lutmasks[quantrant], instr.value>>2, instr.mask>>2, 0, qlut[quantrant], instr.op);
}
this->sync_exec=static_cast<sync_type>(this->sync_exec|core.needed_sync());
}
template<typename ARCH>
std::tuple<vm::continuation_e, llvm::BasicBlock*> vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t& pc, unsigned int& inst_cnt, llvm::BasicBlock* this_block){
// we fetch at max 4 byte, alignment is 2
code_word_t insn = 0;
iss::addr_t paddr;
const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
try {
uint8_t* const data = (uint8_t*)&insn;
paddr=this->core.v2p(pc);
if((pc.val&upper_bits) != ((pc.val+2)&upper_bits)){ // we may cross a page boundary
auto res = this->core.read(paddr, 2, data);
if(res!=iss::Ok)
throw trap_access(1, pc.val);
if((insn & 0x3) == 0x3){ // this is a 32bit instruction
res = this->core.read(this->core.v2p(pc+2), 2, data+2);
}
} else {
auto res = this->core.read(paddr, 4, data);
if(res!=iss::Ok)
throw trap_access(1, pc.val);
}
} catch(trap_access& ta){
throw trap_access(ta.id, pc.val);
}
if(insn==0x0000006f)
throw simulation_stopped(0);
// curr pc on stack
typename vm_impl<ARCH>::processing_pc_entry addr(*this, pc, paddr);
++inst_cnt;
auto lut_val = extract_fields(insn);
auto f = qlut[insn&0x3][lut_val];
if (f==nullptr){
f=&this_class::illegal_intruction;
}
return (this->*f)(pc, insn, this_block);
}
template<typename ARCH>
void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock* leave_blk){
this->builder->SetInsertPoint(leave_blk);
this->builder->CreateRet(this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::NEXT_PC), false));
}
template<typename ARCH>
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause){
auto* TRAP_val = this->gen_const(32, 0x80<<24| (cause<<16) | trap_id );
this->builder->CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
}
template<typename ARCH>
void vm_impl<ARCH>::gen_leave_trap(unsigned lvl){
std::vector<llvm::Value*> args {
this->core_ptr,
llvm::ConstantInt::get(getContext(), llvm::APInt(64, lvl)),
};
this->builder->CreateCall(this->mod->getFunction("leave_trap"), args);
auto* PC_val = this->gen_read_mem(traits<ARCH>::CSR, (lvl<<8)+0x41, traits<ARCH>::XLEN/8);
this->builder->CreateStore(PC_val, get_reg_ptr(traits<ARCH>::NEXT_PC), false);
}
template<typename ARCH>
void vm_impl<ARCH>::gen_wait(unsigned type){
std::vector<llvm::Value*> args {
this->core_ptr,
llvm::ConstantInt::get(getContext(), llvm::APInt(64, type)),
};
this->builder->CreateCall(this->mod->getFunction("wait"), args);
}
template<typename ARCH>
void vm_impl<ARCH>::gen_trap_behavior(llvm::BasicBlock* trap_blk){
this->builder->SetInsertPoint(trap_blk);
auto* trap_state_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
std::vector<llvm::Value*> args {
this->core_ptr,
this->adj_to64(trap_state_val),
this->adj_to64(this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::PC), false))
};
this->builder->CreateCall(this->mod->getFunction("enter_trap"), args);
auto* trap_addr_val = this->builder->CreateLoad(get_reg_ptr(traits<ARCH>::NEXT_PC), false);
this->builder->CreateRet(trap_addr_val);
}
template<typename ARCH> inline
void vm_impl<ARCH>::gen_trap_check(llvm::BasicBlock* bb){
auto* v = this->builder->CreateLoad(get_reg_ptr(arch::traits<ARCH>::TRAP_STATE), true);
this->gen_cond_branch(
this->builder->CreateICmp(
ICmpInst::ICMP_EQ,
v,
llvm::ConstantInt::get(getContext(), llvm::APInt(v->getType()->getIntegerBitWidth(), 0))),
bb,
this->trap_blk, 1);
}
} // namespace CORE_DEF_NAME
#define CREATE_FUNCS(ARCH) \
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, unsigned short port, bool dump) {\
std::unique_ptr<CORE_DEF_NAME::vm_impl<ARCH> > ret = std::make_unique<CORE_DEF_NAME::vm_impl<ARCH> >(*core, dump);\
debugger::server<debugger::gdb_session>::run_server(ret.get(), port);\
return ret;\
}\
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, unsigned short port, bool dump) {\
return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), port, dump); /* FIXME: memory leak!!!!!!! */\
}\
template<> std::unique_ptr<vm_if> create<ARCH>(ARCH* core, bool dump) {\
return std::make_unique<CORE_DEF_NAME::vm_impl<ARCH> >(*core, dump); /* FIXME: memory leak!!!!!!! */ \
}\
template<> std::unique_ptr<vm_if> create<ARCH>(std::string inst_name, bool dump) { \
return create<ARCH>(new arch::riscv_hart_msu_vp<ARCH>(), dump);\
}
CREATE_FUNCS(arch::CORE_DEF_NAME)
namespace CORE_DEF_NAME {
template<typename ARCH>
status target_adapter<ARCH>::set_gen_thread(rp_thread_ref& thread) {
thread_idx=thread;
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::set_ctrl_thread(rp_thread_ref& thread) {
thread_idx=thread;
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::is_thread_alive(rp_thread_ref& thread, bool& alive) {
alive=1;
return Ok;
}
/* List threads. If first is non-zero then start from the first thread,
* otherwise start from arg, result points to array of threads to be
* filled out, result size is number of elements in the result,
* num points to the actual number of threads found, done is
* set if all threads are processed.
*/
template<typename ARCH>
status target_adapter<ARCH>::thread_list_query(int first, const rp_thread_ref& arg, std::vector<rp_thread_ref>& result, size_t max_num,
size_t& num, bool& done) {
if(first==0){
result.clear();
result.push_back(thread_idx);
num=1;
done=true;
return Ok;
} else
return NotSupported;
}
template<typename ARCH>
status target_adapter<ARCH>::current_thread_query(rp_thread_ref& thread) {
thread=thread_idx;
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::read_registers(std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
LOG(logging::TRACE)<<"reading target registers";
//return idx<0?:;
data.clear();
avail.clear();
std::vector<uint8_t> reg_data;
for(size_t reg_no = 0; reg_no < arch::traits<ARCH>::NUM_REGS; ++reg_no){
auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no));
auto reg_width=reg_bit_width/8;
reg_data.resize(reg_width);
vm->get_arch()->get_reg(reg_no, reg_data);
for(size_t j=0; j<reg_data.size(); ++j){
data.push_back(reg_data[j]);
avail.push_back(0xff);
}
}
// work around fill with F type registers
if(arch::traits<ARCH>::NUM_REGS < 65){
auto reg_width=sizeof(typename arch::traits<ARCH>::reg_t);
for(size_t reg_no = 0; reg_no < 33; ++reg_no){
for(size_t j=0; j<reg_width; ++j){
data.push_back(0x0);
avail.push_back(0x00);
}
}
}
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::write_registers(const std::vector<uint8_t>& data) {
size_t data_index=0;
auto reg_count=arch::traits<ARCH>::NUM_REGS;
std::vector<uint8_t> reg_data;
for(size_t reg_no = 0; reg_no < reg_count; ++reg_no){
auto reg_bit_width = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no));
auto reg_width=reg_bit_width/8;
vm->get_arch()->set_reg(reg_no, std::vector<uint8_t>(data.begin()+data_index, data.begin()+data_index+reg_width));
data_index+=reg_width;
}
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::read_single_register(unsigned int reg_no, std::vector<uint8_t>& data, std::vector<uint8_t>& avail) {
if(reg_no<65){
//auto reg_size = arch::traits<ARCH>::reg_bit_width(static_cast<typename arch::traits<ARCH>::reg_e>(reg_no))/8;
data.resize(0);
vm->get_arch()->get_reg(reg_no, data);
avail.resize(data.size());
std::fill(avail.begin(), avail.end(), 0xff);
} else {
typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_READ, traits<ARCH>::CSR, reg_no-65);
data.resize(sizeof(typename traits<ARCH>::reg_t));
avail.resize(sizeof(typename traits<ARCH>::reg_t));
std::fill(avail.begin(), avail.end(), 0xff);
vm->get_arch()->read(a, data.size(), data.data());
}
return data.size()>0?Ok:Err;
}
template<typename ARCH>
status target_adapter<ARCH>::write_single_register(unsigned int reg_no, const std::vector<uint8_t>& data) {
if(reg_no<65)
vm->get_arch()->set_reg(reg_no, data);
else {
typed_addr_t<iss::PHYSICAL> a(iss::DEBUG_WRITE, traits<ARCH>::CSR, reg_no-65);
vm->get_arch()->write(a, data.size(), data.data());
}
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::read_mem(uint64_t addr, std::vector<uint8_t>& data) {
auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
auto f = [&]()->status {
return vm->get_arch()->read(a, data.size(), data.data());
};
return srv->execute_syncronized(f);
}
template<typename ARCH>
status target_adapter<ARCH>::write_mem(uint64_t addr, const std::vector<uint8_t>& data) {
auto a=map_addr({iss::DEBUG_READ, iss::VIRTUAL, 0, addr});
return srv->execute_syncronized(&arch_if::write, vm->get_arch(), a, data.size(), data.data());
}
template<typename ARCH>
status target_adapter<ARCH>::process_query(unsigned int& mask, const rp_thread_ref& arg, rp_thread_info& info) {
return NotSupported;
}
template<typename ARCH>
status target_adapter<ARCH>::offsets_query(uint64_t& text, uint64_t& data, uint64_t& bss) {
text=0;
data=0;
bss=0;
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::crc_query(uint64_t addr, size_t len, uint32_t& val) {
return NotSupported;
}
template<typename ARCH>
status target_adapter<ARCH>::raw_query(std::string in_buf, std::string& out_buf) {
return NotSupported;
}
template<typename ARCH>
status target_adapter<ARCH>::threadinfo_query(int first, std::string& out_buf) {
if(first){
std::stringstream ss;
ss<<"m"<<std::hex<<thread_idx.val;
out_buf=ss.str();
} else {
out_buf="l";
}
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::threadextrainfo_query(const rp_thread_ref& thread, std::string& out_buf) {
char buf[20];
memset(buf, 0, 20);
sprintf (buf, "%02x%02x%02x%02x%02x%02x%02x%02x%02x", 'R', 'u', 'n', 'n', 'a', 'b', 'l', 'e', 0);
out_buf=buf;
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::packetsize_query(std::string& out_buf) {
out_buf="PacketSize=1000";
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::add_break(int type, uint64_t addr, unsigned int length) {
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr});
auto eaddr=map_addr({iss::CODE, iss::PHYSICAL, addr+length});
target_adapter_base::bp_lut.addEntry(++target_adapter_base::bp_count, saddr.val, eaddr.val-saddr.val);
LOG(logging::TRACE)<<"Adding breakpoint with handle "<<target_adapter_base::bp_count<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
LOG(logging::TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
return Ok;
}
template<typename ARCH>
status target_adapter<ARCH>::remove_break(int type, uint64_t addr, unsigned int length) {
auto saddr=map_addr({iss::CODE, iss::PHYSICAL, addr});
unsigned handle=target_adapter_base::bp_lut.getEntry(saddr.val);
// TODO: check length of addr range
if(handle){
LOG(logging::TRACE)<<"Removing breakpoint with handle "<<handle<<" for addr 0x"<<std::hex<<saddr.val<<std::dec;
target_adapter_base::bp_lut.removeEntry(handle);
LOG(logging::TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
return Ok;
}
LOG(logging::TRACE)<<"Now having "<<target_adapter_base::bp_lut.size()<<" breakpoints";
return Err;
}
template<typename ARCH>
status target_adapter<ARCH>::resume_from_addr(bool step, int sig, uint64_t addr) {
unsigned reg_no = arch::traits<ARCH>::PC;
std::vector<uint8_t> data(8);
*(reinterpret_cast<uint64_t*>(&data[0]))=addr;
vm->get_arch()->set_reg(reg_no, data);
return resume_from_current(step, sig);
}
} // namespace CORE_DEF_NAME
} // namespace iss

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riscv.sc/src/internal/vm_rv32imac.cpp Normal file
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3884
riscv.sc/src/internal/vm_rv64ia.cpp Normal file
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76
riscv.sc/src/iss/rv32imac.cpp Normal file
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@ -0,0 +1,76 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Aug 29 16:45:20 CEST 2017
// * rv32imac.cpp Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#include "util/ities.h"
#include <util/logging.h>
#include <elfio/elfio.hpp>
#include <iss/arch/rv32imac.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <ihex.h>
#ifdef __cplusplus
}
#endif
#include <fstream>
#include <cstdio>
#include <cstring>
using namespace iss::arch;
rv32imac::rv32imac() {
reg.icount=0;
}
rv32imac::~rv32imac(){
}
void rv32imac::reset(uint64_t address) {
for(size_t i=0; i<traits<rv32imac>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv32imac>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x3;
}
uint8_t* rv32imac::get_regs_base_ptr(){
return reinterpret_cast<uint8_t*>(&reg);
}
rv32imac::phys_addr_t rv32imac::v2p(const iss::addr_t& pc) {
return phys_addr_t(pc); //change logical address to physical address
}

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@ -0,0 +1,76 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Sep 05 18:57:24 CEST 2017
// * rv64ia.cpp Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#include "util/ities.h"
#include <util/logging.h>
#include <elfio/elfio.hpp>
#include <iss/arch/rv64ia.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <ihex.h>
#ifdef __cplusplus
}
#endif
#include <fstream>
#include <cstdio>
#include <cstring>
using namespace iss::arch;
rv64ia::rv64ia() {
reg.icount=0;
}
rv64ia::~rv64ia(){
}
void rv64ia::reset(uint64_t address) {
for(size_t i=0; i<traits<rv64ia>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
}
uint8_t* rv64ia::get_regs_base_ptr(){
return reinterpret_cast<uint8_t*>(&reg);
}
rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t& pc) {
return phys_addr_t(pc); //change logical address to physical address
}

0
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0
riscv/src/sysc/core_complex.cpp → riscv.sc/src/sysc/core_complex.cpp
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0
riscv/src/sysc/gpio.cpp → riscv.sc/src/sysc/gpio.cpp
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0
riscv/src/sysc/platform.cpp → riscv.sc/src/sysc/platform.cpp
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0
riscv/src/sysc/plic.cpp → riscv.sc/src/sysc/plic.cpp
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0
riscv/src/sysc/spi.cpp → riscv.sc/src/sysc/spi.cpp
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0
riscv/src/sysc/uart.cpp → riscv.sc/src/sysc/uart.cpp
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0
riscv/src/RV32A.core_desc → riscv/gen_input/RV32A.core_desc
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0
riscv/src/RV32C.core_desc → riscv/gen_input/RV32C.core_desc
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0
riscv/src/RV32F.core_desc → riscv/gen_input/RV32F.core_desc
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0
riscv/src/RV32IBase.core_desc → riscv/gen_input/RV32IBase.core_desc
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0
riscv/src/RV32M.core_desc → riscv/gen_input/RV32M.core_desc
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riscv/src/RV64A.core_desc → riscv/gen_input/RV64A.core_desc
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riscv/src/RV64IBase.core_desc → riscv/gen_input/RV64IBase.core_desc
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0
riscv/src/RV64M.core_desc → riscv/gen_input/RV64M.core_desc
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0
riscv/src/minres_rv.core_desc → riscv/gen_input/minres_rv.core_desc
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3
riscv/incl/iss/arch/riscv_hart_msu_vp.h
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@ -523,7 +523,8 @@ protected:
using csr_page_type = typename csr_type::page_type;
mem_type mem;
csr_type csr;
reg_t& mstatus_r, satp_r;
reg_t& mstatus_r;
reg_t& satp_r;
unsigned to_host_wr_cnt=0;
std::stringstream uart_buf;
std::unordered_map<reg_t, uint64_t> ptw;

2
riscv/incl/iss/arch/rv32imac.h
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@ -28,7 +28,7 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Sep 05 18:57:24 CEST 2017
// Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv32imac.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////

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@ -0,0 +1,200 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Thu Sep 21 17:01:54 CEST 2017
// * rv64ia.h Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#ifndef _RV64IA_H_
#define _RV64IA_H_
#include <iss/arch_if.h>
#include <iss/vm_if.h>
#include <iss/arch/traits.h>
namespace iss {
namespace arch {
struct rv64ia;
template<>
struct traits<rv64ia> {
enum constants {XLEN=64,XLEN2=128,XLEN_BIT_MASK=63,PCLEN=64,fence=0,fencei=1,fencevmal=2,fencevmau=3,MISA_VAL=2147750144,PGSIZE=4096,PGMASK=4095};
enum reg_e {
X0,
X1,
X2,
X3,
X4,
X5,
X6,
X7,
X8,
X9,
X10,
X11,
X12,
X13,
X14,
X15,
X16,
X17,
X18,
X19,
X20,
X21,
X22,
X23,
X24,
X25,
X26,
X27,
X28,
X29,
X30,
X31,
PC,
NUM_REGS,
NEXT_PC=NUM_REGS,
TRAP_STATE,
PENDING_TRAP,
MACHINE_STATE,
ICOUNT
};
typedef uint64_t reg_t;
typedef uint64_t addr_t;
typedef uint64_t code_word_t; //TODO: check removal
typedef iss::typed_addr_t<iss::VIRTUAL> virt_addr_t;
typedef iss::typed_addr_t<iss::PHYSICAL> phys_addr_t;
constexpr static unsigned reg_bit_width(unsigned r) {
const uint32_t RV64IA_reg_size[] = {64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,64,32,32,32,64};
return RV64IA_reg_size[r];
}
constexpr static unsigned reg_byte_offset(unsigned r) {
const uint32_t RV64IA_reg_byte_offset[] = {0,8,16,24,32,40,48,56,64,72,80,88,96,104,112,120,128,136,144,152,160,168,176,184,192,200,208,216,224,232,240,248,256,264,272,276,280,288,296};
return RV64IA_reg_byte_offset[r];
}
enum sreg_flag_e {FLAGS};
enum mem_type_e {MEM,CSR,FENCE,RES};
};
struct rv64ia: public arch_if {
using virt_addr_t = typename traits<rv64ia>::virt_addr_t;
using phys_addr_t = typename traits<rv64ia>::phys_addr_t;
using reg_t = typename traits<rv64ia>::reg_t;
using addr_t = typename traits<rv64ia>::addr_t;
rv64ia();
~rv64ia();
virtual void reset(uint64_t address=0) override;
virtual uint8_t* get_regs_base_ptr() override;
/// deprecated
virtual void get_reg(short idx, std::vector<uint8_t>& value) override {}
virtual void set_reg(short idx, const std::vector<uint8_t>& value) override {}
/// deprecated
virtual bool get_flag(int flag) override {return false;}
virtual void set_flag(int, bool value) override {};
/// deprecated
virtual void update_flags(operations op, uint64_t opr1, uint64_t opr2) override {};
virtual void notify_phase(exec_phase phase){
if(phase==ISTART){
++reg.icount;
reg.PC=reg.NEXT_PC;
reg.trap_state=reg.pending_trap;
}
}
uint64_t get_icount() { return reg.icount;}
virtual phys_addr_t v2p(const iss::addr_t& pc);
virtual iss::sync_type needed_sync() const { return iss::PRE_SYNC; }
protected:
struct RV64IA_regs {
uint64_t X0;
uint64_t X1;
uint64_t X2;
uint64_t X3;
uint64_t X4;
uint64_t X5;
uint64_t X6;
uint64_t X7;
uint64_t X8;
uint64_t X9;
uint64_t X10;
uint64_t X11;
uint64_t X12;
uint64_t X13;
uint64_t X14;
uint64_t X15;
uint64_t X16;
uint64_t X17;
uint64_t X18;
uint64_t X19;
uint64_t X20;
uint64_t X21;
uint64_t X22;
uint64_t X23;
uint64_t X24;
uint64_t X25;
uint64_t X26;
uint64_t X27;
uint64_t X28;
uint64_t X29;
uint64_t X30;
uint64_t X31;
uint64_t PC;
uint64_t NEXT_PC;
uint32_t trap_state, pending_trap, machine_state;
uint64_t icount;
} reg;
};
}
}
#endif /* _RV64IA_H_ */

17
riscv/src/CMakeLists.txt
View File

@ -6,21 +6,14 @@ set(LIB_SOURCES
iss/rv64ia.cpp
internal/vm_rv32imac.cpp
internal/vm_rv64ia.cpp
sysc/core_complex.cpp
sysc/gpio.cpp
sysc/plic.cpp
sysc/platform.cpp
sysc/spi.cpp
sysc/uart.cpp
)
set(APP_HEADERS )
set(APP_SOURCES main.cpp sc_main.cpp
)
set(APP_SOURCES main.cpp)
# Define two variables in order not to repeat ourselves.
set(LIBRARY_NAME riscv)
set(LIBRARY_NAME risc-v)
# Define the library
add_library(${LIBRARY_NAME} ${LIB_SOURCES})
@ -32,7 +25,7 @@ set_target_properties(${LIBRARY_NAME} PROPERTIES
)
# This is a make target, so you can do a "make riscv-sc"
set(APPLICATION_NAME riscv-sc)
set(APPLICATION_NAME riscv)
add_executable(${APPLICATION_NAME} ${APP_SOURCES})
@ -42,10 +35,6 @@ target_link_libraries(${APPLICATION_NAME} dbt-core)
target_link_libraries(${APPLICATION_NAME} sc-components)
target_link_libraries(${APPLICATION_NAME} external)
target_link_libraries(${APPLICATION_NAME} ${llvm_libs})
target_link_libraries(${APPLICATION_NAME} ${SystemC_LIBRARIES} )
if(SCV_FOUND)
target_link_libraries (${APPLICATION_NAME} ${SCV_LIBRARIES})
endif()
target_link_libraries(${APPLICATION_NAME} ${Boost_LIBRARIES} )
# Says how and where to install software

190
riscv/src/internal/vm_rv32imac.cpp
View File

@ -227,13 +227,13 @@ protected:
inline
llvm::Value* gen_reg_load(unsigned i, unsigned level=0){
if(level){
// if(level){
return this->builder->CreateLoad(get_reg_ptr(i), false);
} else {
if(!this->loaded_regs[i])
this->loaded_regs[i]=this->builder->CreateLoad(get_reg_ptr(i), false);
return this->loaded_regs[i];
}
// } else {
// if(!this->loaded_regs[i])
// this->loaded_regs[i]=this->builder->CreateLoad(get_reg_ptr(i), false);
// return this->loaded_regs[i];
// }
}
inline
@ -523,7 +523,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LUI x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -556,7 +556,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AUIPC x%1%, 0x%2$08x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -591,7 +591,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("JAL x%1$d, 0x%2$x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -629,7 +629,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("JALR x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -670,7 +670,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BEQ x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -711,7 +711,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BNE x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -752,7 +752,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BLT x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -797,7 +797,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BGE x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -842,7 +842,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BLTU x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -883,7 +883,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("BGEU x%1$d, x%2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -924,7 +924,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LB x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -964,7 +964,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LH x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1004,7 +1004,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LW x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1044,7 +1044,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LBU x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1084,7 +1084,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LHU x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1124,7 +1124,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SB x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1162,7 +1162,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SH x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1200,7 +1200,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SW x%1$d, %2%(x%3$d)");
ins_fmter % (uint64_t)fld_rs2_val % (int64_t)fld_imm_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1238,7 +1238,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("ADDI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1274,7 +1274,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLTI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1319,7 +1319,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLTIU x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1365,7 +1365,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("XORI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1401,7 +1401,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("ORI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1437,7 +1437,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("ANDI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1473,7 +1473,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLLI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1509,7 +1509,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SRLI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1545,7 +1545,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SRAI x%1$d, x%2$d, %3%");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1581,7 +1581,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("ADD x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1617,7 +1617,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SUB x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1653,7 +1653,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLL x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1691,7 +1691,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLT x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1736,7 +1736,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SLTU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1783,7 +1783,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("XOR x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1819,7 +1819,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SRL x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1857,7 +1857,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SRA x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1895,7 +1895,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("OR x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -1931,7 +1931,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AND x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2235,7 +2235,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRW x%1$d, %2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2282,7 +2282,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRS x%1$d, %2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2327,7 +2327,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRC x%1$d, %2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2372,7 +2372,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRWI x%1$d, %2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2414,7 +2414,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRSI x%1$d, %2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2461,7 +2461,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("CSRRCI x%1$d, %2$d, 0x%3$x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_csr_val % (uint64_t)fld_zimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2508,7 +2508,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("MUL x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2554,7 +2554,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("MULH x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2602,7 +2602,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("MULHSU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2650,7 +2650,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("MULHU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2698,7 +2698,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("DIV x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2762,7 +2762,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("DIVU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2826,7 +2826,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("REM x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2890,7 +2890,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("REMU x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -2955,7 +2955,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("LR.W x%1$d, x%2$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3003,7 +3003,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("SC.W x%1$d, x%2$d, x%3$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3068,7 +3068,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOSWAP.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3113,7 +3113,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOADD.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3162,7 +3162,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOXOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3211,7 +3211,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOAND.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3260,7 +3260,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOOR.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3309,7 +3309,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOMIN.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3367,7 +3367,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOMAX.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3425,7 +3425,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOMINU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3479,7 +3479,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("AMOMAXU.W x%1$d, x%2$d, x%3$d (aqu=%4$d,rel=%5$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_aq_val % (uint64_t)fld_rl_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3534,7 +3534,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.ADDI4SPN x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_nzuimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3573,7 +3573,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.LW x(8+%1$d), x(8+%2$d), 0x%3$05x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs1_val % (uint64_t)fld_uimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3610,7 +3610,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SW x(8+%1$d), x(8+%2$d), 0x%3$05x");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_rs2_val % (uint64_t)fld_uimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3648,7 +3648,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.NOP ");
ins_fmter ;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3678,7 +3678,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.ADDI x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_nzimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3713,7 +3713,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.JAL 0x%1$05x");
ins_fmter % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3749,7 +3749,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.LI x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3783,7 +3783,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.LUI x%1$d, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (int64_t)fld_nzimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3822,7 +3822,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.ADDI16SP 0x%1$05x");
ins_fmter % (int64_t)fld_nzimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3858,7 +3858,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SRLI x(8+%1$d), %2$d");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3895,7 +3895,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SRAI x(8+%1$d), %2$d");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3932,7 +3932,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.ANDI x(8+%1$d), 0x%2$05x");
ins_fmter % (uint64_t)fld_rs1_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -3966,7 +3966,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SUB x(8+%1$d), x(8+%2$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4001,7 +4001,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.XOR x(8+%1$d), x(8+%2$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4036,7 +4036,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.OR x(8+%1$d), x(8+%2$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4071,7 +4071,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.AND x(8+%1$d), x(8+%2$d)");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4105,7 +4105,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.J 0x%1$05x");
ins_fmter % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4136,7 +4136,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.BEQZ x(8+%1$d), 0x%2$05x");
ins_fmter % (uint64_t)fld_rs1d_val % (int64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4177,7 +4177,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.BNEZ x(8+%1$d),, 0x%2$05x");
ins_fmter % (uint64_t)fld_rs1d_val % (uint64_t)fld_imm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4218,7 +4218,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SLLI x%1$d, %2$d");
ins_fmter % (uint64_t)fld_rs1_val % (uint64_t)fld_shamt_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4286,7 +4286,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.LWSP x%1$d, sp, 0x%2$05x");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_uimm_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4321,7 +4321,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.MV x%1$d, x%2$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4351,7 +4351,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.JR x%1$d");
ins_fmter % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4406,7 +4406,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.ADD x%1$d, x%2$d");
ins_fmter % (uint64_t)fld_rd_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4438,7 +4438,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.JALR x%1$d");
ins_fmter % (uint64_t)fld_rs1_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4472,7 +4472,7 @@ private:
/* generate console output when executing the command */
boost::format ins_fmter("C.SWSP x2+0x%1$05x, x%2$d");
ins_fmter % (uint64_t)fld_uimm_val % (uint64_t)fld_rs2_val;
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t%%v");
boost::format fmter("0x%1$016x\t\t%2$-40s\t\t");
fmter % pc.val % ins_fmter.str();
std::vector<llvm::Value*> args {
this->core_ptr,
@ -4591,7 +4591,7 @@ void vm_impl<ARCH>::gen_leave_behavior(llvm::BasicBlock* leave_blk){
template<typename ARCH>
void vm_impl<ARCH>::gen_raise_trap(uint16_t trap_id, uint16_t cause){
auto* TRAP_val = this->gen_const(traits<ARCH>::XLEN, 0x80<<24| (cause<<16) | trap_id );
auto* TRAP_val = this->gen_const(32, 0x80<<24| (cause<<16) | trap_id );
this->builder->CreateStore(TRAP_val, get_reg_ptr(traits<ARCH>::TRAP_STATE), true);
}

3884
riscv/src/internal/vm_rv64ia.cpp Normal file
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76
riscv/src/iss/rv64ia.cpp Normal file
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@ -0,0 +1,76 @@
////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// 1. Redistributions of source code must retain the above copyright notice,
// this list of conditions and the following disclaimer.
//
// 2. Redistributions in binary form must reproduce the above copyright notice,
// this list of conditions and the following disclaimer in the documentation
// and/or other materials provided with the distribution.
//
// 3. Neither the name of the copyright holder nor the names of its contributors
// may be used to endorse or promote products derived from this software
// without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
// Created on: Tue Sep 05 18:57:24 CEST 2017
// * rv64ia.cpp Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////
#include "util/ities.h"
#include <util/logging.h>
#include <elfio/elfio.hpp>
#include <iss/arch/rv64ia.h>
#ifdef __cplusplus
extern "C" {
#endif
#include <ihex.h>
#ifdef __cplusplus
}
#endif
#include <fstream>
#include <cstdio>
#include <cstring>
using namespace iss::arch;
rv64ia::rv64ia() {
reg.icount=0;
}
rv64ia::~rv64ia(){
}
void rv64ia::reset(uint64_t address) {
for(size_t i=0; i<traits<rv64ia>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t),0));
reg.PC=address;
reg.NEXT_PC=reg.PC;
reg.trap_state=0;
reg.machine_state=0x0;
}
uint8_t* rv64ia::get_regs_base_ptr(){
return reinterpret_cast<uint8_t*>(&reg);
}
rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t& pc) {
return phys_addr_t(pc); //change logical address to physical address
}

76
riscv/src/main.cpp
View File

@ -40,9 +40,6 @@
#include <iss/arch/rv32imac.h>
#include <iss/arch/rv64ia.h>
#include <iss/jit/MCJIThelper.h>
#ifdef WITH_SYSTEMC
#include <sysc/kernel/sc_externs.h>
#endif
#include <boost/lexical_cast.hpp>
namespace po= boost::program_options;
@ -55,52 +52,43 @@ int main(int argc, char *argv[]) {
if(parse_cli_options(vm, argc, argv)) return ERROR_IN_COMMAND_LINE;
configure_default_logger(vm);
// configure the connection logger
configure_debugger_logger();
configure_debugger_logger();
// application code comes here //
iss::init_jit(argc, argv);
if(vm.count("systemc")){
#ifdef WITH_SYSTEMC
return sc_core::sc_elab_and_sim(argc, argv);
#else
std::cerr<<"SystemC simulation is currently not supported, please rebuild with -DWITH_SYSTEMC"<<std::endl;
#endif
bool dump=vm.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = nullptr;
if(vm.count("rv64")==1){
if(vm.count("gdb-port")==1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump);
} else {
bool dump=vm.count("dump-ir");
// instantiate the simulator
std::unique_ptr<iss::vm_if> cpu = nullptr;
if(vm.count("rv64")==1){
if(vm.count("gdb-port")==1)
cpu = iss::create<iss::arch::rv64ia>("rv64ia", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv64ia>("rv64ia", dump);
} else {
if(vm.count("gdb-port")==1)
cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump);
}
if(vm.count("elf")){
for(std::string input: vm["elf"].as<std::vector<std::string> >())
cpu->get_arch()->load_file(input);
} else if(vm.count("mem")){
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::rv32imac>::MEM);
} //else
// LOG(FATAL)<<"At least one (flash-)input file (ELF or IHEX) needs to be specified";
configure_disass_logger(vm);
if(vm.count("disass")){
cpu->setDisassEnabled(true);
}
if(vm.count("reset")){
auto str = vm["reset"].as<std::string>();
auto start_address = str.find("0x")==0? std::stoull(str, 0, 16):std::stoull(str, 0, 10);
cpu->reset(start_address);
} else {
cpu->reset();
}
return cpu->start(vm["cycles"].as<int64_t>());
if(vm.count("gdb-port")==1)
cpu = iss::create<iss::arch::rv32imac>("rv32ima", vm["gdb-port"].as<unsigned>(), dump);
else
cpu = iss::create<iss::arch::rv32imac>("rv32ima", dump);
}
if(vm.count("elf")){
for(std::string input: vm["elf"].as<std::vector<std::string> >())
cpu->get_arch()->load_file(input);
} else if(vm.count("mem")){
cpu->get_arch()->load_file(vm["mem"].as<std::string>() , iss::arch::traits<iss::arch::rv32imac>::MEM);
}
configure_disass_logger(vm);
if(vm.count("disass")){
cpu->setDisassEnabled(true);
}
if(vm.count("reset")){
auto str = vm["reset"].as<std::string>();
auto start_address = str.find("0x")==0? std::stoull(str, 0, 16):std::stoull(str, 0, 10);
cpu->reset(start_address);
} else {
cpu->reset();
}
return cpu->start(vm["cycles"].as<int64_t>());
} catch(std::exception& e){
LOG(logging::ERROR) << "Unhandled Exception reached the top of main: "
<< e.what() << ", application will now exit" << std::endl;