DBT-RISE/DBT-RISE-TGC
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fixes sysc compile issues

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Eyck Jentzsch
2023-06-12 09:58:24 +02:00
parent 0b5de90fb1
commit 99a9970ddd
4 changed files with 50 additions and 48 deletions
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13
src/iss/arch/riscv_hart_mu_p.h
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@ -284,6 +284,7 @@ public:
}
riscv_hart_mu_p(feature_config cfg = feature_config{});
virtual ~riscv_hart_mu_p() = default;
void reset(uint64_t address) override;
@ -332,17 +333,17 @@ protected:
uint64_t get_next_pc() override { return arch.reg.NEXT_PC; };
uint64_t get_instr_word() override { return arch.instruction; }
uint64_t get_instr_word() override { return arch.reg.instruction; }
uint64_t get_instr_count() override { return arch.icount; }
uint64_t get_instr_count() override { return arch.reg.icount; }
uint64_t get_pendig_traps() override { return arch.trap_state; }
uint64_t get_pendig_traps() override { return arch.reg.trap_state; }
uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; }
uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; }
void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; };
bool is_branch_taken() override { return arch.last_branch; };
bool is_branch_taken() override { return arch.reg.last_branch; };
riscv_hart_mu_p<BASE, FEAT> &arch;
};
@ -949,7 +950,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
res = hart_mem_wr_delegate( phys_addr, length, data);
}
if (unlikely(res != iss::Ok)) {
this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault)
this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr;
}
return res;