From 99a9970ddd37cfcf4a7da8e00f4e35680bdf2a56 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Mon, 12 Jun 2023 09:58:24 +0200 Subject: [PATCH] fixes sysc compile issues --- gen_input/templates/CORENAME_instr.yaml.gtl | 6 +- src/iss/arch/riscv_hart_msu_vp.h | 73 +++++++++++---------- src/iss/arch/riscv_hart_mu_p.h | 13 ++-- src/sysc/core_complex.cpp | 6 +- 4 files changed, 50 insertions(+), 48 deletions(-) diff --git a/gen_input/templates/CORENAME_instr.yaml.gtl b/gen_input/templates/CORENAME_instr.yaml.gtl index 542fed6..eb344ff 100644 --- a/gen_input/templates/CORENAME_instr.yaml.gtl +++ b/gen_input/templates/CORENAME_instr.yaml.gtl @@ -14,7 +14,7 @@ ${name}: <% instrList.findAll{!it.instruction.name.startsWith("__")}.each { %> encoding: ${it.encoding} mask: ${it.mask}<%if(it.attributes.size) {%> attributes: ${it.attributes}<%}%> - size: ${it.length} - branch: ${it.modifiesPC} - delay: ${it.isConditional?"[1,1]":"1"}<%}}%> + size: ${it.length} + branch: ${it.modifiesPC} + delay: ${it.isConditional?"[1,1]":"1"}<%}}%> diff --git a/src/iss/arch/riscv_hart_msu_vp.h b/src/iss/arch/riscv_hart_msu_vp.h index 49d1363..24ce7f0 100644 --- a/src/iss/arch/riscv_hart_msu_vp.h +++ b/src/iss/arch/riscv_hart_msu_vp.h @@ -316,6 +316,9 @@ public: csr[addr & csr.page_addr_mask] = val; } + void set_irq_num(unsigned i) { + mcause_max_irq=1<::core_type; } - virtual uint64_t get_pc() { return arch.get_pc(); }; + uint64_t get_pc() override { return arch.reg.PC; }; - virtual uint64_t get_next_pc() { return arch.get_next_pc(); }; + uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }; - uint64_t get_instr_word() override { return arch.instruction; } + uint64_t get_instr_word() override { return arch.reg.instruction; } - uint64_t get_instr_count() { return arch.icount; } + uint64_t get_instr_count() override { return arch.reg.icount; } - uint64_t get_pendig_traps() override { return arch.trap_state; } + uint64_t get_pendig_traps() override { return arch.reg.trap_state; } - uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; } + uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; } void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }; - bool is_branch_taken() override { return arch.last_branch; }; + bool is_branch_taken() override { return arch.reg.last_branch; }; riscv_hart_msu_vp &arch; }; @@ -381,16 +384,17 @@ protected: std::unordered_map csr_rd_cb; std::unordered_map csr_wr_cb; -private: - iss::status read_reg(unsigned addr, reg_t &val); - iss::status write_reg(unsigned addr, reg_t val); + std::vector tcm; + + iss::status read_csr_reg(unsigned addr, reg_t &val); + iss::status write_csr_reg(unsigned addr, reg_t val); iss::status read_null(unsigned addr, reg_t &val); iss::status write_null(unsigned addr, reg_t val){return iss::status::Ok;} iss::status read_cycle(unsigned addr, reg_t &val); iss::status write_cycle(unsigned addr, reg_t val); iss::status read_instret(unsigned addr, reg_t &val); iss::status write_instret(unsigned addr, reg_t val); - iss::status read_mtvec(unsigned addr, reg_t &val); + iss::status read_tvec(unsigned addr, reg_t &val); iss::status read_time(unsigned addr, reg_t &val); iss::status read_status(unsigned addr, reg_t &val); iss::status write_status(unsigned addr, reg_t val); @@ -398,6 +402,8 @@ private: iss::status read_ie(unsigned addr, reg_t &val); iss::status write_ie(unsigned addr, reg_t val); iss::status read_ip(unsigned addr, reg_t &val); + iss::status write_ideleg(unsigned addr, reg_t val); + iss::status write_edeleg(unsigned addr, reg_t val); iss::status read_hartid(unsigned addr, reg_t &val); iss::status write_epc(unsigned addr, reg_t val); iss::status read_satp(unsigned addr, reg_t &val); @@ -417,7 +423,6 @@ private: reg_t mhartid_reg{0x0}; -protected: void check_interrupt(); }; @@ -434,22 +439,22 @@ riscv_hart_msu_vp::riscv_hart_msu_vp() uart_buf.str(""); for (unsigned addr = mhpmcounter3; addr <= mhpmcounter31; ++addr){ csr_rd_cb[addr] = &this_class::read_null; - csr_wr_cb[addr] = &this_class::write_reg; + csr_wr_cb[addr] = &this_class::write_csr_reg; } for (unsigned addr = mhpmcounter3h; addr <= mhpmcounter31h; ++addr){ csr_rd_cb[addr] = &this_class::read_null; - csr_wr_cb[addr] = &this_class::write_reg; + csr_wr_cb[addr] = &this_class::write_csr_reg; } for (unsigned addr = mhpmevent3; addr <= mhpmevent31; ++addr){ csr_rd_cb[addr] = &this_class::read_null; - csr_wr_cb[addr] = &this_class::write_reg; + csr_wr_cb[addr] = &this_class::write_csr_reg; } for (unsigned addr = hpmcounter3; addr <= hpmcounter31; ++addr){ csr_rd_cb[addr] = &this_class::read_null; } for (unsigned addr = cycleh; addr <= hpmcounter31h; ++addr){ csr_rd_cb[addr] = &this_class::read_null; - //csr_wr_cb[addr] = &this_class::write_reg; + //csr_wr_cb[addr] = &this_class::write_csr_reg; } // common regs const std::array addrs{{ @@ -459,25 +464,25 @@ riscv_hart_msu_vp::riscv_hart_msu_vp() uepc, utvec, uscratch, ucause, utval, uscratch }}; for(auto addr: addrs) { - csr_rd_cb[addr] = &this_class::read_reg; - csr_wr_cb[addr] = &this_class::write_reg; + csr_rd_cb[addr] = &this_class::read_csr_reg; + csr_wr_cb[addr] = &this_class::write_csr_reg; } // special handling & overrides csr_rd_cb[time] = &this_class::read_time; - csr_rd_cb[timeh] = &this_class::read_time; + if(traits::XLEN==32) csr_rd_cb[timeh] = &this_class::read_time; csr_rd_cb[cycle] = &this_class::read_cycle; - csr_rd_cb[cycleh] = &this_class::read_cycle; + if(traits::XLEN==32) csr_rd_cb[cycleh] = &this_class::read_cycle; csr_rd_cb[instret] = &this_class::read_instret; - csr_rd_cb[instreth] = &this_class::read_instret; + if(traits::XLEN==32) csr_rd_cb[instreth] = &this_class::read_instret; csr_rd_cb[mcycle] = &this_class::read_cycle; csr_wr_cb[mcycle] = &this_class::write_cycle; - csr_rd_cb[mcycleh] = &this_class::read_cycle; - csr_wr_cb[mcycleh] = &this_class::write_cycle; + if(traits::XLEN==32) csr_rd_cb[mcycleh] = &this_class::read_cycle; + if(traits::XLEN==32) csr_wr_cb[mcycleh] = &this_class::write_cycle; csr_rd_cb[minstret] = &this_class::read_instret; csr_wr_cb[minstret] = &this_class::write_instret; - csr_rd_cb[minstreth] = &this_class::read_instret; - csr_wr_cb[minstreth] = &this_class::write_instret; + if(traits::XLEN==32) csr_rd_cb[minstreth] = &this_class::read_instret; + if(traits::XLEN==32) csr_wr_cb[minstreth] = &this_class::write_instret; csr_rd_cb[mstatus] = &this_class::read_status; csr_wr_cb[mstatus] = &this_class::write_status; csr_wr_cb[mcause] = &this_class::write_cause; @@ -527,10 +532,10 @@ template std::pair riscv_hart_msu_vp::load if (fp) { std::array buf; auto n = fread(buf.data(), 1, 4, fp); + fclose(fp); if (n != 4) throw std::runtime_error("input file has insufficient size"); buf[4] = 0; if (strcmp(buf.data() + 1, "ELF") == 0) { - fclose(fp); // Create elfio reader ELFIO::elfio reader; // Load ELF data @@ -549,7 +554,7 @@ template std::pair riscv_hart_msu_vp::load traits::MEM, pseg->get_physical_address(), fsize, reinterpret_cast(seg_data)); if (res != iss::Ok) - LOG(ERROR) << "problem writing " << fsize << "bytes to 0x" << std::hex + LOG(ERR) << "problem writing " << fsize << "bytes to 0x" << std::hex << pseg->get_physical_address(); } } @@ -673,7 +678,7 @@ iss::status riscv_hart_msu_vp::read(const address_type type, const access_ } return iss::Ok; } catch (trap_access &ta) { - this->reg.trap_state = (1 << 31) | ta.id; + this->reg.trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; } @@ -730,12 +735,12 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access write_mem(phys_addr_t{access, space, addr}, length, data): write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data); if (unlikely(res != iss::Ok)) { - this->reg.trap_state = (1 << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) + this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault) fault_data=addr; } return res; } catch (trap_access &ta) { - this->reg.trap_state = (1 << 31) | ta.id; + this->reg.trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; } @@ -800,7 +805,7 @@ iss::status riscv_hart_msu_vp::write(const address_type type, const access } return iss::Ok; } catch (trap_access &ta) { - this->reg.trap_state = (1 << 31) | ta.id; + this->reg.trap_state = (1UL << 31) | ta.id; fault_data=ta.addr; return iss::Err; } @@ -858,8 +863,6 @@ template iss::status riscv_hart_msu_vp::read_cycle(unsigne template iss::status riscv_hart_msu_vp::write_cycle(unsigned addr, reg_t val) { if (sizeof(typename traits::reg_t) != 4) { - if (addr == mcycleh) - return iss::Err; mcycle_csr = static_cast(val); } else { if (addr == mcycle) { @@ -876,7 +879,6 @@ template iss::status riscv_hart_msu_vp::read_instret(unsig if ((addr&0xff) == (minstret&0xff)) { val = static_cast(this->reg.instret); } else if ((addr&0xff) == (minstreth&0xff)) { - if (sizeof(typename traits::reg_t) != 4) return iss::Err; val = static_cast(this->reg.instret >> 32); } return iss::Ok; @@ -884,8 +886,6 @@ template iss::status riscv_hart_msu_vp::read_instret(unsig template iss::status riscv_hart_msu_vp::write_instret(unsigned addr, reg_t val) { if (sizeof(typename traits::reg_t) != 4) { - if ((addr&0xff) == (minstreth&0xff)) - return iss::Err; this->reg.instret = static_cast(val); } else { if ((addr&0xff) == (minstret&0xff)) { @@ -1234,6 +1234,7 @@ template uint64_t riscv_hart_msu_vp::enter_trap(uint64_t f auto cur_priv = this->reg.PRIV; // flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0] // calculate and write mcause val + if(flags==std::numeric_limits::max()) flags=this->reg.trap_state; auto trap_id = bit_sub<0, 16>(flags); auto cause = bit_sub<16, 15>(flags); if (trap_id == 0 && cause == 11) cause = 0x8 + cur_priv; // adjust environment call cause diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 0dc0de7..9650ee5 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -284,6 +284,7 @@ public: } riscv_hart_mu_p(feature_config cfg = feature_config{}); + virtual ~riscv_hart_mu_p() = default; void reset(uint64_t address) override; @@ -332,17 +333,17 @@ protected: uint64_t get_next_pc() override { return arch.reg.NEXT_PC; }; - uint64_t get_instr_word() override { return arch.instruction; } + uint64_t get_instr_word() override { return arch.reg.instruction; } - uint64_t get_instr_count() override { return arch.icount; } + uint64_t get_instr_count() override { return arch.reg.icount; } - uint64_t get_pendig_traps() override { return arch.trap_state; } + uint64_t get_pendig_traps() override { return arch.reg.trap_state; } - uint64_t get_total_cycles() override { return arch.icount + arch.cycle_offset; } + uint64_t get_total_cycles() override { return arch.reg.icount + arch.cycle_offset; } void update_last_instr_cycles(unsigned cycles) override { arch.cycle_offset += cycles - 1; }; - bool is_branch_taken() override { return arch.last_branch; }; + bool is_branch_taken() override { return arch.reg.last_branch; }; riscv_hart_mu_p &arch; }; @@ -949,7 +950,7 @@ iss::status riscv_hart_mu_p::write(const address_type type, const ac res = hart_mem_wr_delegate( phys_addr, length, data); } if (unlikely(res != iss::Ok)) { - this->reg.trap_state = (1UL << 31) | (7 << 16); // issue trap 7 (Store/AMO access fault) + this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault) fault_data=addr; } return res; diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index f3a7ae4..b135117 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -118,7 +118,7 @@ public: std::stringstream s; s << "[p:" << lvl[this->reg.PRIV] << ";s:0x" << std::hex << std::setfill('0') << std::setw(sizeof(reg_t) * 2) << (reg_t)this->state.mstatus << std::dec << ";c:" - << this->icount + this->cycle_offset << "]"; + << this->reg.icount + this->cycle_offset << "]"; SCCDEBUG(owner->name())<<"disass: " << "0x" << std::setw(16) << std::right << std::setfill('0') << std::hex << pc << "\t\t" << std::setw(40) << std::setfill(' ') << std::left << instr << s.str(); @@ -178,7 +178,7 @@ public: void wait_until(uint64_t flags) override { SCCDEBUG(owner->name()) << "Sleeping until interrupt"; - while(this->pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) { + while(this->reg.pending_trap == 0 && (this->csr[arch::mip] & this->csr[arch::mie]) == 0) { sc_core::wait(wfi_evt); } PLAT::wait_until(flags); @@ -207,7 +207,7 @@ public: this->csr[arch::mip] &= ~mask; this->check_interrupt(); if(value) - SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->pending_trap; + SCCTRACE(owner->name()) << "Triggering interrupt " << id << " Pending trap: " << this->reg.pending_trap; } private: