re-introduces last_branch register
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32848ec396
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95ba5c901a
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@ -34,6 +34,7 @@ def getRegisterSizes(){
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def regs = registers.collect{it.size}
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def regs = registers.collect{it.size}
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regs[-1]=64 // correct for NEXT_PC
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regs[-1]=64 // correct for NEXT_PC
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//regs+=[32, 32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
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//regs+=[32, 32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
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regs += [32] // append LAST_BRANCH
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return regs
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return regs
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}
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}
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%>
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%>
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@ -38,6 +38,7 @@ def nativeTypeSize(int size){
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def getRegisterSizes(){
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def getRegisterSizes(){
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def regs = registers.collect{nativeTypeSize(it.size)}
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def regs = registers.collect{nativeTypeSize(it.size)}
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// regs+=[32,32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
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// regs+=[32,32, 64, 64, 64, 32] // append TRAP_STATE, PENDING_TRAP, ICOUNT, CYCLE, INSTRET, INSTRUCTION
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regs += [32] // append LAST_BRANCH
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return regs
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return regs
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}
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}
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def getRegisterOffsets(){
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def getRegisterOffsets(){
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@ -91,7 +92,7 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
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constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
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constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
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enum reg_e {
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enum reg_e {
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${registers.collect{it.name}.join(', ')}, NUM_REGS
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${registers.collect{it.name}.join(', ')}, NUM_REGS, LAST_BRANCH=NUM_REGS
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};
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};
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using reg_t = uint${addrDataWidth}_t;
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using reg_t = uint${addrDataWidth}_t;
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@ -162,6 +163,7 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
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registers.each { reg -> if(reg.size>0) {%>
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registers.each { reg -> if(reg.size>0) {%>
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uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
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uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
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}}%>
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}}%>
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uint32_t last_branch = 0;
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} reg;
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} reg;
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#pragma pack(pop)
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#pragma pack(pop)
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uint32_t trap_state = 0, pending_trap = 0;
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uint32_t trap_state = 0, pending_trap = 0;
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