regenerated sources and and add opcode enum to headers

Conflicts: gen_input/CoreDSL-Instruction-Set-Description
2021-03-01 06:26:33 +00:00
parent 1668df0531
commit 9534d58d01
17 changed files with 361 additions and 609 deletions
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -33,7 +33,7 @@
 def getRegisterSizes(){
 	def regs = registers.collect{it.size}
 	regs[-1]=64 // correct for NEXT_PC
-	regs+=[32, 32, 32, 32, 64] // append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT
+	regs+=[32, 32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
    return regs
 }
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