DBT-RISE/DBT-RISE-TGC
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regenerated sources and and add opcode enum to headers

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Conflicts:
	gen_input/CoreDSL-Instruction-Set-Description
This commit is contained in:
Eyck Jentzsch
2021-03-01 06:26:33 +00:00
parent 1668df0531
commit 9534d58d01
17 changed files with 361 additions and 609 deletions
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2
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -33,7 +33,7 @@
def getRegisterSizes(){
def regs = registers.collect{it.size}
regs[-1]=64 // correct for NEXT_PC
regs+=[32, 32, 32, 32, 64] // append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT
regs+=[32, 32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
return regs
}
%>

37
gen_input/templates/interp/CORENAME.h.gtl
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@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2017 - 2020 MINRES Technologies GmbH
* Copyright (C) 2017 - 2021 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -29,22 +29,23 @@
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
<%
<%
def nativeTypeSize(int size){
if(size<=8) return 8; else if(size<=16) return 16; else if(size<=32) return 32; else return 64;
}
def getRegisterSizes(){
def regs = registers.collect{it.size}
regs[-1]=pc.size // correct for NEXT_PC
regs+=[32, 32, 32, 32, 64] // append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT
def regs = registers.collect{nativeTypeSize(it.size)}
regs+=[32,32, 64] // append TRAP_STATE, PENDING_TRAP, ICOUNT
return regs
}
def getRegisterOffsets(){
def regs = registers.collect{it.offset}
def offs= regs[-1]
// append TRAP_STATE, PENDING_TRAP, MACHINE_STATE, LAST_BRANCH, ICOUNT offsets starting with NEXT_PC size
[pc.size/8, 4, 4, 4, 4].each{ sz ->
regs+=offs+sz
offs+=sz
def offset = 0
def offsets = []
getRegisterSizes().each { size ->
offsets<<offset
offset+=size/8
}
return regs
return offsets
}
def byteSize(int size){
if(size<=8) return 8;
@ -81,15 +82,10 @@ template <> struct traits<${coreDef.name.toLowerCase()}> {
constexpr static unsigned FP_REGS_SIZE = ${constants.find {it.name=='FLEN'}?.value?:0};
enum reg_e {<%
registers.each { reg -> %>
${reg.name},<%
}%>
NEXT_${pc.name}=NUM_REGS,
TRAP_STATE,
enum reg_e {
${registers.collect{it.name}.join(', ')}, NUM_REGS,
TRAP_STATE=NUM_REGS,
PENDING_TRAP,
MACHINE_STATE,
LAST_BRANCH,
ICOUNT
};
@ -168,7 +164,6 @@ protected:
registers.each { reg -> if(reg.size>0) {%>
uint${byteSize(reg.size)}_t ${reg.name} = 0;<%
}}%>
uint${byteSize(pc.size)}_t NEXT_${pc.name} = 0;
uint32_t trap_state = 0, pending_trap = 0, machine_state = 0, last_branch = 0;
uint64_t icount = 0;
} reg;

13
gen_input/templates/interp/vm_CORENAME.cpp.gtl
View File

@ -1,5 +1,5 @@
/*******************************************************************************
* Copyright (C) 2020 MINRES Technologies GmbH
* Copyright (C) 2021 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
@ -149,13 +149,14 @@ protected:
this->core.leave_trap(lvl);
auto pc_val = super::template read_mem<reg_t>(traits::CSR, (lvl << 8) + 0x41);
this->template get_reg<reg_t>(traits::NEXT_PC) = pc_val;
this->template get_reg<uint32_t>(traits::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
}
void wait(unsigned type){
this->core.wait_until(type);
}
template<typename T>
T& pc_assign(T& val){super::ex_info.branch_taken=true; return val;}
inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint8_t>(space, addr);}
inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint16_t>(space, addr);}
inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint32_t>(space, addr);}
@ -196,17 +197,15 @@ private:
// prepare execution
uint${addrDataWidth}_t* X = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint${addrDataWidth}_t* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
uint${addrDataWidth}_t* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
*NEXT_PC = *PC + ${instr.length/8};
// execute instruction
<%instr.behavior.eachLine{%>${it}
<%}%>// post execution stuff<% if(instr.modifiesPC) { %>
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);<% } else { %>
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + ${instr.length/8};<% } %>
<%}%>// post execution stuff
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);