Strip down privileged modes. Only machine mode is supported
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969b408288
commit
6f3963a473
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@ -174,8 +174,6 @@ enum riscv_csr {
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namespace {
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std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
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std::array<const char *, 16> trap_str = {{""
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"Instruction address misaligned", // 0
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"Instruction access fault", // 1
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@ -326,8 +324,8 @@ public:
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static const reg_t mstatus_reset_val = 0;
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void write_mstatus(T val, unsigned priv_lvl) {
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auto mask = get_mask(priv_lvl);
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void write_mstatus(T val) {
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auto mask = get_mask();
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auto new_val = (mstatus.st.value & ~mask) | (val & mask);
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mstatus = new_val;
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}
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@ -336,41 +334,19 @@ public:
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static constexpr T get_misa() { return (1UL << 30) | ISA_I | ISA_M | ISA_A | ISA_U | ISA_S | ISA_M; }
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static constexpr uint32_t get_mask(unsigned priv_lvl) {
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#if __cplusplus < 201402L
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return priv_lvl == PRIV_U ? 0x80000011UL : priv_lvl == PRIV_S ? 0x800de133UL : 0x807ff9ddUL;
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#else
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switch (priv_lvl) {
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case PRIV_U: return 0x80000011UL; // 0b1000 0000 0000 0000 0000 0000 0001 0001
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case PRIV_S: return 0x800de133UL; // 0b1000 0000 0000 1101 1110 0001 0011 0011
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default: return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011
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}
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#endif
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static constexpr uint32_t get_mask() {
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return 0x807ff9ddUL; // 0b1000 0000 0111 1111 1111 1001 1011 1011 // only machine mode is supported
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}
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static inline vm_info decode_vm_info(uint32_t state, T sptbr) {
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if (state == PRIV_M) return {0, 0, 0, 0};
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if (state <= PRIV_S)
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switch (bit_sub<31, 1>(sptbr)) {
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case 0: return {0, 0, 0, 0}; // off
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case 1: return {2, 10, 4, bit_sub<0, 22>(sptbr) << PGSHIFT}; // SV32
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default: abort();
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}
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abort();
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return {0, 0, 0, 0}; // dummy
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static inline vm_info decode_vm_info() {
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return {0, 0, 0, 0};
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}
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};
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const typename super::reg_t PGSIZE = 1 << PGSHIFT;
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const typename super::reg_t PGMASK = PGSIZE - 1;
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constexpr reg_t get_irq_mask(size_t mode) {
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std::array<const reg_t, 4> m = {{
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0b000100010001, // U mode
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0b001100110011, // S mode
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0,
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0b101110111011 // M mode
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}};
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return m[mode];
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constexpr reg_t get_irq_mask() {
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return 0b101110111011; // only machine mode is supported
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}
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riscv_hart_m_p();
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@ -396,8 +372,8 @@ public:
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void set_mhartid(reg_t mhartid) { mhartid_reg = mhartid; };
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void disass_output(uint64_t pc, const std::string instr) override {
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CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [p:{};s:0x{:x};c:{}]",
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pc, instr, lvl[this->reg.machine_state], (reg_t)state.mstatus, this->reg.icount);
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CLOG(INFO, disass) << fmt::format("0x{:016x} {:40} [s:0x{:x};c:{}]",
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pc, instr, (reg_t)state.mstatus, this->reg.icount);
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};
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iss::instrumentation_if *get_instrumentation_if() override { return &instr_if; }
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@ -497,22 +473,10 @@ riscv_hart_m_p<BASE>::riscv_hart_m_p()
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csr_rd_cb[minstreth] = &riscv_hart_m_p<BASE>::read_cycle;
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csr_rd_cb[mstatus] = &riscv_hart_m_p<BASE>::read_status;
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csr_wr_cb[mstatus] = &riscv_hart_m_p<BASE>::write_status;
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csr_rd_cb[sstatus] = &riscv_hart_m_p<BASE>::read_status;
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csr_wr_cb[sstatus] = &riscv_hart_m_p<BASE>::write_status;
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csr_rd_cb[ustatus] = &riscv_hart_m_p<BASE>::read_status;
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csr_wr_cb[ustatus] = &riscv_hart_m_p<BASE>::write_status;
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csr_rd_cb[mip] = &riscv_hart_m_p<BASE>::read_ip;
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csr_wr_cb[mip] = &riscv_hart_m_p<BASE>::write_ip;
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csr_rd_cb[sip] = &riscv_hart_m_p<BASE>::read_ip;
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csr_wr_cb[sip] = &riscv_hart_m_p<BASE>::write_ip;
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csr_rd_cb[uip] = &riscv_hart_m_p<BASE>::read_ip;
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csr_wr_cb[uip] = &riscv_hart_m_p<BASE>::write_ip;
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csr_rd_cb[mie] = &riscv_hart_m_p<BASE>::read_ie;
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csr_wr_cb[mie] = &riscv_hart_m_p<BASE>::write_ie;
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csr_rd_cb[sie] = &riscv_hart_m_p<BASE>::read_ie;
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csr_wr_cb[sie] = &riscv_hart_m_p<BASE>::write_ie;
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csr_rd_cb[uie] = &riscv_hart_m_p<BASE>::read_ie;
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csr_wr_cb[uie] = &riscv_hart_m_p<BASE>::write_ie;
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csr_rd_cb[mhartid] = &riscv_hart_m_p<BASE>::read_hartid;
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}
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@ -583,7 +547,7 @@ iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_typ
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}
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try {
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if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
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vm_info vm = hart_state<reg_t>::decode_vm_info(this->reg.machine_state, state.satp);
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vm_info vm = hart_state<reg_t>::decode_vm_info();
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if (vm.levels != 0) { // VM is active
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auto split_addr = (addr + length) & ~PGMASK;
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auto len1 = split_addr - addr;
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@ -609,18 +573,7 @@ iss::status riscv_hart_m_p<BASE>::read(const address_type type, const access_typ
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} break;
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case traits<BASE>::FENCE: {
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if ((addr + length) > mem.size()) return iss::Err;
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switch (addr) {
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case 2: // SFENCE:VMA lower
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case 3: { // SFENCE:VMA upper
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auto tvm = state.mstatus.TVM;
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if (this->reg.machine_state == PRIV_S & tvm != 0) {
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this->reg.trap_state = (1 << 31) | (2 << 16);
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this->fault_data = this->reg.PC;
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return iss::Err;
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}
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return iss::Ok;
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}
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}
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} break;
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case traits<BASE>::RES: {
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auto it = atomic_reservation.find(addr);
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@ -677,7 +630,7 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
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}
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try {
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if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
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vm_info vm = hart_state<reg_t>::decode_vm_info(this->reg.machine_state, state.satp);
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vm_info vm = hart_state<reg_t>::decode_vm_info();
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if (vm.levels != 0) { // VM is active
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auto split_addr = (addr + length) & ~PGMASK;
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auto len1 = split_addr - addr;
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@ -741,11 +694,6 @@ iss::status riscv_hart_m_p<BASE>::write(const address_type type, const access_ty
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case 3: {
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ptw.clear();
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auto tvm = state.mstatus.TVM;
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if (this->reg.machine_state == PRIV_S & tvm != 0) {
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this->reg.trap_state = (1 << 31) | (2 << 16);
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this->fault_data = this->reg.PC;
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return iss::Err;
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}
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return iss::Ok;
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}
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}
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@ -817,14 +765,12 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_time(unsigned ad
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_status(unsigned addr, reg_t &val) {
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auto req_priv_lvl = (addr >> 8) & 0x3;
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val = state.mstatus & hart_state<reg_t>::get_mask(req_priv_lvl);
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val = state.mstatus & hart_state<reg_t>::get_mask();
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned addr, reg_t val) {
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auto req_priv_lvl = (addr >> 8) & 0x3;
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state.write_mstatus(val, req_priv_lvl);
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state.write_mstatus(val);
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check_interrupt();
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update_vm_info();
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return iss::Ok;
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@ -832,8 +778,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_status(unsigned
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ie(unsigned addr, reg_t &val) {
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val = csr[mie];
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if (addr < mie) val &= csr[mideleg];
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if (addr < sie) val &= csr[sideleg];
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val &= csr[mideleg];
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return iss::Ok;
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}
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@ -843,8 +788,7 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_hartid(unsigned
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned addr, reg_t val) {
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auto req_priv_lvl = (addr >> 8) & 0x3;
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auto mask = get_irq_mask(req_priv_lvl);
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auto mask = get_irq_mask();
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csr[mie] = (csr[mie] & ~mask) | (val & mask);
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check_interrupt();
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return iss::Ok;
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@ -852,76 +796,18 @@ template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ie(unsigned add
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_ip(unsigned addr, reg_t &val) {
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val = csr[mip];
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if (addr < mip) val &= csr[mideleg];
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if (addr < sip) val &= csr[sideleg];
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val &= csr[mideleg];
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_ip(unsigned addr, reg_t val) {
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auto req_priv_lvl = (addr >> 8) & 0x3;
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auto mask = get_irq_mask(req_priv_lvl);
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auto mask = get_irq_mask();
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mask &= ~(1 << 7); // MTIP is read only
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csr[mip] = (csr[mip] & ~mask) | (val & mask);
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check_interrupt();
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_satp(unsigned addr, reg_t &val) {
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reg_t tvm = state.mstatus.TVM;
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if (this->reg.machine_state == PRIV_S & tvm != 0) {
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this->reg.trap_state = (1 << 31) | (2 << 16);
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this->fault_data = this->reg.PC;
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return iss::Err;
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}
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val = state.satp;
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_satp(unsigned addr, reg_t val) {
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reg_t tvm = state.mstatus.TVM;
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if (this->reg.machine_state == PRIV_S & tvm != 0) {
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this->reg.trap_state = (1 << 31) | (2 << 16);
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this->fault_data = this->reg.PC;
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return iss::Err;
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}
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state.satp = val;
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update_vm_info();
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::read_fcsr(unsigned addr, reg_t &val) {
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switch (addr) {
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case 1: // fflags, 4:0
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val = bit_sub<0, 5>(this->get_fcsr());
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break;
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case 2: // frm, 7:5
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val = bit_sub<5, 3>(this->get_fcsr());
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break;
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case 3: // fcsr
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val = this->get_fcsr();
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break;
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default:
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return iss::Err;
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}
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return iss::Ok;
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}
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template <typename BASE> iss::status riscv_hart_m_p<BASE>::write_fcsr(unsigned addr, reg_t val) {
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switch (addr) {
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case 1: // fflags, 4:0
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this->set_fcsr((this->get_fcsr() & 0xffffffe0) | (val & 0x1f));
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break;
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case 2: // frm, 7:5
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this->set_fcsr((this->get_fcsr() & 0xffffff1f) | ((val & 0x7) << 5));
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break;
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case 3: // fcsr
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this->set_fcsr(val & 0xff);
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break;
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default:
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return iss::Err;
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}
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return iss::Ok;
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}
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template <typename BASE>
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iss::status riscv_hart_m_p<BASE>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
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if ((paddr.val + length) > mem.size()) return iss::Err;
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@ -1032,10 +918,10 @@ template <typename BASE> inline void riscv_hart_m_p<BASE>::reset(uint64_t addres
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}
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template <typename BASE> inline void riscv_hart_m_p<BASE>::update_vm_info() {
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vm[1] = hart_state<reg_t>::decode_vm_info(this->reg.machine_state, state.satp);
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vm[1] = hart_state<reg_t>::decode_vm_info();
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BASE::addr_mode[3]=BASE::addr_mode[2] = vm[1].is_active()? iss::address_type::VIRTUAL : iss::address_type::PHYSICAL;
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if (state.mstatus.MPRV)
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vm[0] = hart_state<reg_t>::decode_vm_info(state.mstatus.MPP, state.satp);
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vm[0] = hart_state<reg_t>::decode_vm_info();
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else
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vm[0] = vm[1];
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BASE::addr_mode[1] = BASE::addr_mode[0]=vm[0].is_active() ? iss::address_type::VIRTUAL : iss::address_type::PHYSICAL;
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@ -1057,11 +943,6 @@ template <typename BASE> void riscv_hart_m_p<BASE>::check_interrupt() {
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auto m_enabled = this->reg.machine_state < PRIV_M || (this->reg.machine_state == PRIV_M && mie);
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auto enabled_interrupts = m_enabled ? ena_irq & ~ideleg : 0;
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if (enabled_interrupts == 0) {
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auto sie = state.mstatus.SIE;
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auto s_enabled = this->reg.machine_state < PRIV_S || (this->reg.machine_state == PRIV_S && sie);
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enabled_interrupts = s_enabled ? ena_irq & ideleg : 0;
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}
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if (enabled_interrupts != 0) {
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int res = 0;
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while ((enabled_interrupts & 1) == 0) enabled_interrupts >>= 1, res++;
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@ -1094,7 +975,6 @@ typename riscv_hart_m_p<BASE>::phys_addr_t riscv_hart_m_p<BASE>::virt2phys(const
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const vm_info &vm = this->vm[static_cast<uint16_t>(type) / 2];
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const bool s_mode = mode == PRIV_S;
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const bool sum = state.mstatus.SUM;
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const bool mxr = state.mstatus.MXR;
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@ -1118,7 +998,7 @@ typename riscv_hart_m_p<BASE>::phys_addr_t riscv_hart_m_p<BASE>::virt2phys(const
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if (PTE_TABLE(pte)) { // next level of page table
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base = ppn << PGSHIFT;
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} else if ((pte & PTE_U) ? s_mode && (type == iss::access_type::FETCH || !sum) : !s_mode) {
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} else if (!(pte & PTE_U)) {
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break;
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} else if (!(pte & PTE_V) || (!(pte & PTE_R) && (pte & PTE_W))) {
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break;
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@ -1163,36 +1043,22 @@ typename riscv_hart_m_p<BASE>::phys_addr_t riscv_hart_m_p<BASE>::virt2phys(const
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}
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template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flags, uint64_t addr) {
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auto cur_priv = this->reg.machine_state;
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// flags are ACTIVE[31:31], CAUSE[30:16], TRAPID[15:0]
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// calculate and write mcause val
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auto trap_id = bit_sub<0, 16>(flags);
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auto cause = bit_sub<16, 15>(flags);
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if (trap_id == 0 && cause == 11) cause = 0x8 + cur_priv; // adjust environment call cause
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if (trap_id == 0 && cause == 11) cause = 0x8 + PRIV_M; // adjust environment call cause
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// calculate effective privilege level
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auto new_priv = PRIV_M;
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if (trap_id == 0) { // exception
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if (cur_priv != PRIV_M && ((csr[medeleg] >> cause) & 0x1) != 0)
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new_priv = (csr[sedeleg] >> cause) & 0x1 ? PRIV_U : PRIV_S;
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// store ret addr in xepc register
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csr[uepc | (new_priv << 8)] = static_cast<reg_t>(addr); // store actual address instruction of exception
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/*
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* write mtval if new_priv=M_MODE, spec says:
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* When a hardware breakpoint is triggered, or an instruction-fetch, load,
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* or store address-misaligned,
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* access, or page-fault exception occurs, mtval is written with the
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* faulting effective address.
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*/
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csr[utval | (new_priv << 8)] = fault_data;
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csr[mepc] = static_cast<reg_t>(addr); // store actual address instruction of exception
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csr[mtval] = fault_data;
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fault_data = 0;
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} else {
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if (cur_priv != PRIV_M && ((csr[mideleg] >> cause) & 0x1) != 0)
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new_priv = (csr[sideleg] >> cause) & 0x1 ? PRIV_U : PRIV_S;
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csr[uepc | (new_priv << 8)] = this->reg.NEXT_PC; // store next address if interrupt
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csr[mepc] = this->reg.NEXT_PC; // store next address if interrupt
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this->reg.pending_trap = 0;
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}
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size_t adr = ucause | (new_priv << 8);
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csr[adr] = (trap_id << 31) + cause;
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csr[mcause] = (trap_id << 31) + cause;
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// update mstatus
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||||
// xPP field of mstatus is written with the active privilege mode at the time
|
||||
// of the trap; the x PIE field of mstatus
|
||||
|
|
@ -1200,41 +1066,25 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::enter_trap(uint64_t flag
|
|||
// the trap; and the x IE field of mstatus
|
||||
// is cleared
|
||||
// store the actual privilege level in yPP and store interrupt enable flags
|
||||
switch (new_priv) {
|
||||
case PRIV_M:
|
||||
state.mstatus.MPP = cur_priv;
|
||||
state.mstatus.MPP = PRIV_M;
|
||||
state.mstatus.MPIE = state.mstatus.MIE;
|
||||
state.mstatus.MIE = false;
|
||||
break;
|
||||
case PRIV_S:
|
||||
state.mstatus.SPP = cur_priv;
|
||||
state.mstatus.SPIE = state.mstatus.SIE;
|
||||
state.mstatus.SIE = false;
|
||||
break;
|
||||
case PRIV_U:
|
||||
state.mstatus.UPIE = state.mstatus.UIE;
|
||||
state.mstatus.UIE = false;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
// get trap vector
|
||||
auto ivec = csr[utvec | (new_priv << 8)];
|
||||
auto ivec = csr[mtvec];
|
||||
// calculate addr// set NEXT_PC to trap addressess to jump to based on MODE
|
||||
// bits in mtvec
|
||||
this->reg.NEXT_PC = ivec & ~0x1UL;
|
||||
if ((ivec & 0x1) == 1 && trap_id != 0) this->reg.NEXT_PC += 4 * cause;
|
||||
// reset trap state
|
||||
this->reg.machine_state = new_priv;
|
||||
this->reg.machine_state = PRIV_M;
|
||||
this->reg.trap_state = 0;
|
||||
std::array<char, 32> buffer;
|
||||
sprintf(buffer.data(), "0x%016lx", addr);
|
||||
if((flags&0xffffffff) != 0xffffffff)
|
||||
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
|
||||
<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << cause << ")"
|
||||
<< " at address " << buffer.data() << " occurred, changing privilege level from "
|
||||
<< lvl[cur_priv] << " to " << lvl[new_priv];
|
||||
<< " at address " << buffer.data() << " occurred";
|
||||
update_vm_info();
|
||||
return this->reg.NEXT_PC;
|
||||
}
|
||||
|
|
@ -1244,47 +1094,24 @@ template <typename BASE> uint64_t riscv_hart_m_p<BASE>::leave_trap(uint64_t flag
|
|||
auto inst_priv = flags & 0x3;
|
||||
auto status = state.mstatus;
|
||||
|
||||
auto tsr = state.mstatus.TSR;
|
||||
if (cur_priv == PRIV_S && inst_priv == PRIV_S && tsr != 0) {
|
||||
this->reg.trap_state = (1 << 31) | (2 << 16);
|
||||
this->fault_data = this->reg.PC;
|
||||
return this->reg.PC;
|
||||
}
|
||||
|
||||
// pop the relevant lower-privilege interrupt enable and privilege mode stack
|
||||
// clear respective yIE
|
||||
switch (inst_priv) {
|
||||
case PRIV_M:
|
||||
if (inst_priv == PRIV_M) {
|
||||
this->reg.machine_state = state.mstatus.MPP;
|
||||
state.mstatus.MPP = 0; // clear mpp to U mode
|
||||
state.mstatus.MIE = state.mstatus.MPIE;
|
||||
break;
|
||||
case PRIV_S:
|
||||
this->reg.machine_state = state.mstatus.SPP;
|
||||
state.mstatus.SPP = 0; // clear spp to U mode
|
||||
state.mstatus.SIE = state.mstatus.SPIE;
|
||||
break;
|
||||
case PRIV_U:
|
||||
this->reg.machine_state = 0;
|
||||
state.mstatus.UIE = state.mstatus.UPIE;
|
||||
break;
|
||||
} else {
|
||||
CLOG(ERROR, disass) << "Unsupported mode:" << inst_priv;
|
||||
}
|
||||
|
||||
// sets the pc to the value stored in the x epc register.
|
||||
this->reg.NEXT_PC = csr[uepc | inst_priv << 8];
|
||||
CLOG(INFO, disass) << "Executing xRET , changing privilege level from " << lvl[cur_priv] << " to "
|
||||
<< lvl[this->reg.machine_state];
|
||||
this->reg.NEXT_PC = csr[mepc];
|
||||
CLOG(INFO, disass) << "Executing xRET";
|
||||
update_vm_info();
|
||||
return this->reg.NEXT_PC;
|
||||
}
|
||||
|
||||
template <typename BASE> void riscv_hart_m_p<BASE>::wait_until(uint64_t flags) {
|
||||
auto status = state.mstatus;
|
||||
auto tw = status.TW;
|
||||
if (this->reg.machine_state == PRIV_S && tw != 0) {
|
||||
this->reg.trap_state = (1 << 31) | (2 << 16);
|
||||
this->fault_data = this->reg.PC;
|
||||
}
|
||||
}
|
||||
template <typename BASE> void riscv_hart_m_p<BASE>::wait_until(uint64_t flags) {}
|
||||
} // namespace arch
|
||||
} // namespace iss
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue