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DBT-RISE-TGC
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fixes WFI miss of interrupt

This commit is contained in:
Eyck Jentzsch 2023-01-14 17:40:21 +01:00
parent 3187cbdfe2
commit 65dca13b42
2 changed files with 6 additions and 4 deletions
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5
gen_input/templates/interp/CORENAME.cpp.gtl
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@ -289,8 +289,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// post execution stuff // post execution stuff
process_spawn_blocks(); process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id)); if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
if(!this->core.trap_state) // update trap state if there is a pending interrupt // if(!this->core.trap_state) // update trap state if there is a pending interrupt
this->core.trap_state = this->core.pending_trap; // this->core.trap_state = this->core.pending_trap;
// trap check // trap check
if(trap_state!=0){ if(trap_state!=0){
super::core.enter_trap(trap_state, pc.val, instr); super::core.enter_trap(trap_state, pc.val, instr);
@ -301,6 +301,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
cycle++; cycle++;
pc.val=*NEXT_PC; pc.val=*NEXT_PC;
this->core.reg.PC = this->core.reg.NEXT_PC; this->core.reg.PC = this->core.reg.NEXT_PC;
this->core.trap_state = this->core.pending_trap;
} }
} }
return pc; return pc;

5
src/vm/interp/vm_tgc_c.cpp
View File

@ -2538,8 +2538,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// post execution stuff // post execution stuff
process_spawn_blocks(); process_spawn_blocks();
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id)); if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
if(!this->core.trap_state) // update trap state if there is a pending interrupt // if(!this->core.trap_state) // update trap state if there is a pending interrupt
this->core.trap_state = this->core.pending_trap; // this->core.trap_state = this->core.pending_trap;
// trap check // trap check
if(trap_state!=0){ if(trap_state!=0){
super::core.enter_trap(trap_state, pc.val, instr); super::core.enter_trap(trap_state, pc.val, instr);
@ -2550,6 +2550,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
cycle++; cycle++;
pc.val=*NEXT_PC; pc.val=*NEXT_PC;
this->core.reg.PC = this->core.reg.NEXT_PC; this->core.reg.PC = this->core.reg.NEXT_PC;
this->core.trap_state = this->core.pending_trap;
} }
} }
return pc; return pc;