diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl
index 3b62ca7..4b84520 100644
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -289,8 +289,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             // post execution stuff
             process_spawn_blocks();
             if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
-            if(!this->core.trap_state) // update trap state if there is a pending interrupt
-                this->core.trap_state = this->core.pending_trap;
+            // if(!this->core.trap_state) // update trap state if there is a pending interrupt
+            //    this->core.trap_state = this->core.pending_trap;
             // trap check
             if(trap_state!=0){
                 super::core.enter_trap(trap_state, pc.val, instr);
@@ -301,6 +301,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             cycle++;
             pc.val=*NEXT_PC;
             this->core.reg.PC = this->core.reg.NEXT_PC;
+            this->core.trap_state = this->core.pending_trap;
         }
     }
     return pc;
diff --git a/src/vm/interp/vm_tgc_c.cpp b/src/vm/interp/vm_tgc_c.cpp
index 826c770..9ef0760 100644
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
@@ -2538,8 +2538,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             // post execution stuff
             process_spawn_blocks();
             if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(inst_id));
-            if(!this->core.trap_state) // update trap state if there is a pending interrupt
-                this->core.trap_state = this->core.pending_trap;
+            // if(!this->core.trap_state) // update trap state if there is a pending interrupt
+            //    this->core.trap_state = this->core.pending_trap;
             // trap check
             if(trap_state!=0){
                 super::core.enter_trap(trap_state, pc.val, instr);
@@ -2550,6 +2550,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
             cycle++;
             pc.val=*NEXT_PC;
             this->core.reg.PC = this->core.reg.NEXT_PC;
+            this->core.trap_state = this->core.pending_trap;
         }
     }
     return pc;