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DBT-RISE-TGC
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fix linker issue 

the root cuase of the issue is the template paramter deduction which led
to the wrong template parameter.
This commit is contained in:
Eyck Jentzsch 2021-06-26 14:30:36 +02:00
parent a249aea703
commit 5d8da08ce5
5 changed files with 19 additions and 21 deletions
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8
incl/iss/arch/riscv_hart_m_p.h
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@ -91,11 +91,11 @@ protected:
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
public: public:
using super = BASE; using core = BASE;
using this_class = riscv_hart_m_p<BASE>; using this_class = riscv_hart_m_p<BASE>;
using phys_addr_t = typename super::phys_addr_t; using phys_addr_t = typename core::phys_addr_t;
using reg_t = typename super::reg_t; using reg_t = typename core::reg_t;
using addr_t = typename super::addr_t; using addr_t = typename core::addr_t;
using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &); using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);

14
incl/iss/arch/riscv_hart_msu_vp.h
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@ -90,12 +90,12 @@ protected:
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
public: public:
using super = BASE; using core = BASE;
using this_class = riscv_hart_msu_vp<BASE>; using this_class = riscv_hart_msu_vp<BASE>;
using virt_addr_t = typename super::virt_addr_t; using virt_addr_t = typename core::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t; using phys_addr_t = typename core::phys_addr_t;
using reg_t = typename super::reg_t; using reg_t = typename core::reg_t;
using addr_t = typename super::addr_t; using addr_t = typename core::addr_t;
using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &); using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);
@ -272,8 +272,8 @@ public:
}; };
using hart_state_type = hart_state<reg_t>; using hart_state_type = hart_state<reg_t>;
const typename super::reg_t PGSIZE = 1 << PGSHIFT; const typename core::reg_t PGSIZE = 1 << PGSHIFT;
const typename super::reg_t PGMASK = PGSIZE - 1; const typename core::reg_t PGMASK = PGSIZE - 1;
constexpr reg_t get_irq_mask(size_t mode) { constexpr reg_t get_irq_mask(size_t mode) {
std::array<const reg_t, 4> m = {{ std::array<const reg_t, 4> m = {{

8
incl/iss/arch/riscv_hart_mu_p.h
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@ -93,11 +93,11 @@ protected:
"User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt",
"User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}};
public: public:
using super = BASE; using core = BASE;
using this_class = riscv_hart_mu_p<BASE, FEAT>; using this_class = riscv_hart_mu_p<BASE, FEAT>;
using phys_addr_t = typename super::phys_addr_t; using phys_addr_t = typename core::phys_addr_t;
using reg_t = typename super::reg_t; using reg_t = typename core::reg_t;
using addr_t = typename super::addr_t; using addr_t = typename core::addr_t;
using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &); using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &);
using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t);

2
incl/iss/factory.h
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@ -42,7 +42,7 @@ using vm_ptr= std::unique_ptr<iss::vm_if>;
template<typename PLAT> template<typename PLAT>
std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){ std::tuple<cpu_ptr, vm_ptr> create_cpu(std::string const& backend, unsigned gdb_port){
using core_type = typename PLAT::super; using core_type = typename PLAT::core;
core_type* lcpu = new PLAT(); core_type* lcpu = new PLAT();
if(backend == "interp") if(backend == "interp")
return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}}; return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}};

8
src/sysc/core_complex.cpp
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@ -36,11 +36,9 @@
#include "iss/arch/tgc_b.h" #include "iss/arch/tgc_b.h"
using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>; using tgc_b_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_b>;
#endif #endif
#ifdef CORE_TGC_C
#include "iss/arch/riscv_hart_m_p.h" #include "iss/arch/riscv_hart_m_p.h"
#include "iss/arch/tgc_c.h" #include "iss/arch/tgc_c.h"
using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>; using tgc_c_plat_type = iss::arch::riscv_hart_m_p<iss::arch::tgc_c>;
#endif
#ifdef CORE_TGC_D #ifdef CORE_TGC_D
#include "iss/arch/riscv_hart_mu_p.h" #include "iss/arch/riscv_hart_mu_p.h"
#include "iss/arch/tgc_d.h" #include "iss/arch/tgc_d.h"
@ -81,8 +79,8 @@ std::array<const char, 4> lvl = {{'U', 'S', 'H', 'M'}};
template<typename PLAT> template<typename PLAT>
class core_wrapper_t : public PLAT { class core_wrapper_t : public PLAT {
public: public:
using reg_t = typename arch::traits<typename PLAT::super>::reg_t; using reg_t = typename arch::traits<typename PLAT::core>::reg_t;
using phys_addr_t = typename arch::traits<typename PLAT::super>::phys_addr_t; using phys_addr_t = typename arch::traits<typename PLAT::core>::phys_addr_t;
using heart_state_t = typename PLAT::hart_state_type; using heart_state_t = typename PLAT::hart_state_type;
core_wrapper_t(core_complex *owner) core_wrapper_t(core_complex *owner)
: owner(owner) { } : owner(owner) { }
@ -248,7 +246,7 @@ public:
set_interrupt_execution = [lcpu](bool b) { return lcpu->set_interrupt_execution(b); }; set_interrupt_execution = [lcpu](bool b) { return lcpu->set_interrupt_execution(b); };
local_irq = [lcpu](short s, bool b) { return lcpu->local_irq(s, b); }; local_irq = [lcpu](short s, bool b) { return lcpu->local_irq(s, b); };
if(backend == "interp") if(backend == "interp")
return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}}; return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(static_cast<typename PLAT::core*>(lcpu), gdb_port)}};
#ifdef WITH_LLVM #ifdef WITH_LLVM
if(backend == "llvm") if(backend == "llvm")
return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}}; return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};