From 5d8da08ce5b7cf917037bf693719ef5ca6ec6a93 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Sat, 26 Jun 2021 14:30:36 +0200 Subject: [PATCH] fix linker issue the root cuase of the issue is the template paramter deduction which led to the wrong template parameter. --- incl/iss/arch/riscv_hart_m_p.h | 8 ++++---- incl/iss/arch/riscv_hart_msu_vp.h | 14 +++++++------- incl/iss/arch/riscv_hart_mu_p.h | 8 ++++---- incl/iss/factory.h | 2 +- src/sysc/core_complex.cpp | 8 +++----- 5 files changed, 19 insertions(+), 21 deletions(-) diff --git a/incl/iss/arch/riscv_hart_m_p.h b/incl/iss/arch/riscv_hart_m_p.h index a0230f9..5920915 100644 --- a/incl/iss/arch/riscv_hart_m_p.h +++ b/incl/iss/arch/riscv_hart_m_p.h @@ -91,11 +91,11 @@ protected: "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; public: - using super = BASE; + using core = BASE; using this_class = riscv_hart_m_p; - using phys_addr_t = typename super::phys_addr_t; - using reg_t = typename super::reg_t; - using addr_t = typename super::addr_t; + using phys_addr_t = typename core::phys_addr_t; + using reg_t = typename core::reg_t; + using addr_t = typename core::addr_t; using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &); using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); diff --git a/incl/iss/arch/riscv_hart_msu_vp.h b/incl/iss/arch/riscv_hart_msu_vp.h index 0c86afe..8e4577e 100644 --- a/incl/iss/arch/riscv_hart_msu_vp.h +++ b/incl/iss/arch/riscv_hart_msu_vp.h @@ -90,12 +90,12 @@ protected: "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; public: - using super = BASE; + using core = BASE; using this_class = riscv_hart_msu_vp; - using virt_addr_t = typename super::virt_addr_t; - using phys_addr_t = typename super::phys_addr_t; - using reg_t = typename super::reg_t; - using addr_t = typename super::addr_t; + using virt_addr_t = typename core::virt_addr_t; + using phys_addr_t = typename core::phys_addr_t; + using reg_t = typename core::reg_t; + using addr_t = typename core::addr_t; using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &); using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); @@ -272,8 +272,8 @@ public: }; using hart_state_type = hart_state; - const typename super::reg_t PGSIZE = 1 << PGSHIFT; - const typename super::reg_t PGMASK = PGSIZE - 1; + const typename core::reg_t PGSIZE = 1 << PGSHIFT; + const typename core::reg_t PGMASK = PGSIZE - 1; constexpr reg_t get_irq_mask(size_t mode) { std::array m = {{ diff --git a/incl/iss/arch/riscv_hart_mu_p.h b/incl/iss/arch/riscv_hart_mu_p.h index 6ca3906..1fb583c 100644 --- a/incl/iss/arch/riscv_hart_mu_p.h +++ b/incl/iss/arch/riscv_hart_mu_p.h @@ -93,11 +93,11 @@ protected: "User timer interrupt", "Supervisor timer interrupt", "Reserved", "Machine timer interrupt", "User external interrupt", "Supervisor external interrupt", "Reserved", "Machine external interrupt"}}; public: - using super = BASE; + using core = BASE; using this_class = riscv_hart_mu_p; - using phys_addr_t = typename super::phys_addr_t; - using reg_t = typename super::reg_t; - using addr_t = typename super::addr_t; + using phys_addr_t = typename core::phys_addr_t; + using reg_t = typename core::reg_t; + using addr_t = typename core::addr_t; using rd_csr_f = iss::status (this_class::*)(unsigned addr, reg_t &); using wr_csr_f = iss::status (this_class::*)(unsigned addr, reg_t); diff --git a/incl/iss/factory.h b/incl/iss/factory.h index 266ff31..1664e38 100644 --- a/incl/iss/factory.h +++ b/incl/iss/factory.h @@ -42,7 +42,7 @@ using vm_ptr= std::unique_ptr; template std::tuple create_cpu(std::string const& backend, unsigned gdb_port){ - using core_type = typename PLAT::super; + using core_type = typename PLAT::core; core_type* lcpu = new PLAT(); if(backend == "interp") return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}}; diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp index cc201a2..4bbc3a5 100644 --- a/src/sysc/core_complex.cpp +++ b/src/sysc/core_complex.cpp @@ -36,11 +36,9 @@ #include "iss/arch/tgc_b.h" using tgc_b_plat_type = iss::arch::riscv_hart_m_p; #endif -#ifdef CORE_TGC_C #include "iss/arch/riscv_hart_m_p.h" #include "iss/arch/tgc_c.h" using tgc_c_plat_type = iss::arch::riscv_hart_m_p; -#endif #ifdef CORE_TGC_D #include "iss/arch/riscv_hart_mu_p.h" #include "iss/arch/tgc_d.h" @@ -81,8 +79,8 @@ std::array lvl = {{'U', 'S', 'H', 'M'}}; template class core_wrapper_t : public PLAT { public: - using reg_t = typename arch::traits::reg_t; - using phys_addr_t = typename arch::traits::phys_addr_t; + using reg_t = typename arch::traits::reg_t; + using phys_addr_t = typename arch::traits::phys_addr_t; using heart_state_t = typename PLAT::hart_state_type; core_wrapper_t(core_complex *owner) : owner(owner) { } @@ -248,7 +246,7 @@ public: set_interrupt_execution = [lcpu](bool b) { return lcpu->set_interrupt_execution(b); }; local_irq = [lcpu](short s, bool b) { return lcpu->local_irq(s, b); }; if(backend == "interp") - return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(lcpu, gdb_port)}}; + return {cpu_ptr{lcpu}, vm_ptr{iss::interp::create(static_cast(lcpu), gdb_port)}}; #ifdef WITH_LLVM if(backend == "llvm") return {cpu_ptr{lcpu}, vm_ptr{iss::llvm::create(lcpu, gdb_port)}};