moves common functionality to base class
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@ -2695,11 +2695,12 @@ std::unique_ptr<vm_if> create<arch::tgc5c>(arch::tgc5c *core, unsigned short por
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} // namespace iss
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#include <iss/arch/riscv_hart_m_p.h>
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#include <iss/arch/riscv_hart_msu_vp.h>
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#include <iss/arch/riscv_hart_mu_p.h>
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#include <iss/factory.h>
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namespace iss {
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namespace {
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volatile std::array<bool, 2> dummy = {
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volatile std::array<bool, 3> dummy = {
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core_factory::instance().register_creator("tgc5c|m_p|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto* cpu = new iss::arch::riscv_hart_m_p<iss::arch::tgc5c>();
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auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
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@ -2719,6 +2720,16 @@ volatile std::array<bool, 2> dummy = {
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cpu->set_semihosting_callback(*cb);
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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}),
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core_factory::instance().register_creator("tgc5c|mus_vp|interp", [](unsigned port, void* init_data) -> std::tuple<cpu_ptr, vm_ptr>{
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auto* cpu = new iss::arch::riscv_hart_msu_vp<iss::arch::tgc5c>();
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auto vm = new interp::tgc5c::vm_impl<arch::tgc5c>(*cpu, false);
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
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if(init_data){
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auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::tgc5c>::reg_t>*>(init_data);
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cpu->set_semihosting_callback(*cb);
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}
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return {cpu_ptr{cpu}, vm_ptr{vm}};
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})
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};
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}
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