DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

[WIP] update dependencies in core desc

Browse Source
This commit is contained in:
Eyck Jentzsch
2020-06-18 06:18:59 +02:00
parent c619194465
commit 55450f4900
8 changed files with 3683 additions and 3969 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
gen_input/RVC.core_desc
View File

@ -171,7 +171,7 @@ InsructionSet RV32IC extends RISCVBase{
}
}
InsructionSet RV32FC extends RV32IC{
InsructionSet RV32FC extends RISCVBase{
constants {
FLEN
}
@ -218,7 +218,7 @@ InsructionSet RV32FC extends RV32IC{
}
}
InsructionSet RV32DC extends RV32IC{
InsructionSet RV32DC extends RISCVBase{
constants {
FLEN
}
@ -306,6 +306,12 @@ InsructionSet RV64IC extends RV32IC {
val rs1_idx[5] <= rs1+8;
X[rs1_idx] <= shrl(X[rs1_idx], shamt);
}
C.SRLI64 {//(RV64)
encoding:b1000 | b00 | rs1[2:0] | 00000 | b01;
args_disass: "{name(8+rs1)}, {shamt}";
val rs1_idx[5] <= rs1+8;
X[rs1_idx] <= shrl(X[rs1_idx], shamt);
}
C.SRAI {//(RV64)
encoding:b100 | shamt[5:5] | b01 | rs1[2:0] | shamt[4:0] | b01;
args_disass: "{name(8+rs1)}, {shamt}";