refactored interpreter backend structure
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b37ef973de
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521f40a3d6
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@ -94,7 +94,7 @@ protected:
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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compile_func decode_inst(code_word_t instr) ;
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typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
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virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
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// some compile time constants
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@ -114,7 +114,7 @@ protected:
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struct instruction_pattern {
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uint32_t value;
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uint32_t mask;
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compile_func opc;
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typename arch::traits<ARCH>::opcode_e id;
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};
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std::array<std::vector<instruction_pattern>, 4> qlut;
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@ -201,74 +201,14 @@ private:
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size_t length;
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uint32_t value;
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uint32_t mask;
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compile_func op;
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typename arch::traits<ARCH>::opcode_e op;
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};
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const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
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/* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
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/* instruction ${instr.instruction.name} */
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{${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
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{${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
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}};
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/* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
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/* instruction ${idx}: ${instr.name} */
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compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
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// pre execution stuff
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if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, ${idx});
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<%instr.fields.eachLine{%>${it}
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<%}%>if(this->disass_enabled){
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/* generate console output when executing the command */
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<%instr.disass.eachLine{%>${it}
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<%}%>
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}
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auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
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auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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// used registers<%instr.usedVariables.each{ k,v->
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if(v.isArray) {%>
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auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
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auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
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<%}}%>// calculate next pc value
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*NEXT_PC = *PC + ${instr.length/8};
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// execute instruction
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try {
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<%instr.behavior.eachLine{%>${it}
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<%}%>} catch(...){}
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// post execution stuff
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process_spawn_blocks();
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
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// trap check
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if(*trap_state!=0){
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super::core.enter_trap(*trap_state, pc.val, instr);
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} else {
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(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
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(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
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}
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(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
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pc.val=*NEXT_PC;
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return pc;
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}
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<%}%>
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/****************************************************************************
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* end opcode definitions
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****************************************************************************/
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compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
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this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
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uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
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uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
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raise(0, 2);
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// post execution stuff
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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// trap check
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if(*trap_state!=0){
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super::core.enter_trap(*trap_state, pc.val, instr);
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}
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pc.val=*NEXT_PC;
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return pc;
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}
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//static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
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iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
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auto phys_pc = this->core.v2p(pc);
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@ -307,6 +247,7 @@ constexpr size_t bit_count(uint32_t u) {
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template <typename ARCH>
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vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
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: vm_base<ARCH>(core, core_id, cluster_id) {
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unsigned id=0;
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for (auto instr : instr_descr) {
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auto quadrant = instr.value & 0x3;
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qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
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@ -327,31 +268,74 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
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}
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template <typename ARCH>
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typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
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typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
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for(auto& e: qlut[instr&0x3]){
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if(!((instr&e.mask) ^ e.value )) return e.opc;
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if(!((instr&e.mask) ^ e.value )) return e.id;
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}
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return &this_class::illegal_intruction;
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return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
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}
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template <typename ARCH>
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typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
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// we fetch at max 4 byte, alignment is 2
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code_word_t insn = 0;
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auto *const data = (uint8_t *)&insn;
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code_word_t instr = 0;
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auto *const data = (uint8_t *)&instr;
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auto pc=start;
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auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
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auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
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auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
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auto* icount = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]);
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auto* instret = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]);
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while(!this->core.should_stop() &&
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!(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
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auto res = fetch_ins(pc, data);
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if(res!=iss::Ok){
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if(fetch_ins(pc, data)!=iss::Ok){
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this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
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pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
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} else {
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if (is_jump_to_self_enabled(cond) &&
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(insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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auto f = decode_inst(insn);
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auto old_pc = pc.val;
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pc = (this->*f)(pc, insn);
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(instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
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auto inst_id = decode_inst_id(instr);
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// pre execution stuff
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if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
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switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
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case arch::traits<ARCH>::opcode_e::${instr.name}: {
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<%instr.fields.eachLine{%>${it}
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<%}%>if(this->disass_enabled){
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/* generate console output when executing the command */
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<%instr.disass.eachLine{%>${it}
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<%}%>
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}
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// used registers<%instr.usedVariables.each{ k,v->
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if(v.isArray) {%>
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auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %>
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auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
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<%}}%>// calculate next pc value
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*NEXT_PC = *PC + ${instr.length/8};
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// execute instruction
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try {
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<%instr.behavior.eachLine{%>${it}
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<%}%>} catch(...){}
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}
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break;<%}%>
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default: {
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*NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
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raise(0, 2);
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}
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}
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// post execution stuff
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process_spawn_blocks();
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if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
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// trap check
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if(*trap_state!=0){
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super::core.enter_trap(*trap_state, pc.val, instr);
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} else {
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(*icount)++;
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(*instret)++;
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}
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(*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
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pc.val=*NEXT_PC;
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this->core.reg.PC = this->core.reg.NEXT_PC;
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this->core.reg.trap_state = this->core.reg.pending_trap;
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}
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@ -359,7 +343,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
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return pc;
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}
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} // namespace mnrv32
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}
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template <>
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std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
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