From 521f40a3d6c390c6c3f35f38ccae34777b4b40db Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 5 Mar 2022 20:59:17 +0100
Subject: [PATCH] refactored interpreter backend structure

---
 gen_input/templates/interp/CORENAME.cpp.gtl |  136 +-
 src/vm/interp/vm_tgc_c.cpp                  | 6092 +++++++------------
 2 files changed, 2208 insertions(+), 4020 deletions(-)

diff --git a/gen_input/templates/interp/CORENAME.cpp.gtl b/gen_input/templates/interp/CORENAME.cpp.gtl
index 119c084..084bafd 100644
--- a/gen_input/templates/interp/CORENAME.cpp.gtl
+++ b/gen_input/templates/interp/CORENAME.cpp.gtl
@@ -94,7 +94,7 @@ protected:
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
-    compile_func decode_inst(code_word_t instr) ;
+    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
@@ -114,7 +114,7 @@ protected:
     struct instruction_pattern {
         uint32_t value;
         uint32_t mask;
-        compile_func opc;
+        typename arch::traits<ARCH>::opcode_e id;
     };
 
     std::array<std::vector<instruction_pattern>, 4> qlut;
@@ -201,73 +201,13 @@ private:
         size_t length;
         uint32_t value;
         uint32_t mask;
-        compile_func op;
+        typename arch::traits<ARCH>::opcode_e op;
     };
 
     const std::array<InstructionDesriptor, ${instructions.size}> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */<%instructions.each{instr -> %>
-        /* instruction ${instr.instruction.name} */
-        {${instr.length}, ${instr.encoding}, ${instr.mask}, &this_class::__${generator.functionName(instr.name)}},<%}%>
+        {${instr.length}, ${instr.encoding}, ${instr.mask}, arch::traits<ARCH>::opcode_e::${instr.instruction.name}},<%}%>
     }};
- 
-    /* instruction definitions */<%instructions.eachWithIndex{instr, idx -> %>
-    /* instruction ${idx}: ${instr.name} */
-    compile_ret_t __${generator.functionName(instr.name)}(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, ${idx});
-        <%instr.fields.eachLine{%>${it}
-        <%}%>if(this->disass_enabled){
-            /* generate console output when executing the command */
-            <%instr.disass.eachLine{%>${it}
-            <%}%>
-        }
-        auto* PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint${addrDataWidth}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers<%instr.usedVariables.each{ k,v->
-            if(v.isArray) {%>
-        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
-        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
-        <%}}%>// calculate next pc value
-        *NEXT_PC = *PC + ${instr.length/8};
-        // execute instruction
-        try {
-        <%instr.behavior.eachLine{%>${it}
-        <%}%>} catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, ${idx});
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    <%}%>
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
-        this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
-        raise(0,  2);
-        // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        }
-        pc.val=*NEXT_PC;
-        return pc;
-    }
 
     //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
@@ -307,6 +247,7 @@ constexpr size_t bit_count(uint32_t u) {
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
+    unsigned id=0;
     for (auto instr : instr_descr) {
         auto quadrant = instr.value & 0x3;
         qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
@@ -327,31 +268,74 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
 }
 
 template <typename ARCH>
-typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
+typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
     for(auto& e: qlut[instr&0x3]){
-        if(!((instr&e.mask) ^ e.value )) return e.opc;
+        if(!((instr&e.mask) ^ e.value )) return e.id;
     }
-    return &this_class::illegal_intruction;
+    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
 }
 
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
     // we fetch at max 4 byte, alignment is 2
-    code_word_t insn = 0;
-    auto *const data = (uint8_t *)&insn;
+    code_word_t instr = 0;
+    auto *const data = (uint8_t *)&instr;
     auto pc=start;
+
+    auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+    auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
+    auto* icount = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]);
+    auto* instret = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]);
+
     while(!this->core.should_stop() &&
             !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
-        auto res = fetch_ins(pc, data);
-        if(res!=iss::Ok){
+        if(fetch_ins(pc, data)!=iss::Ok){
             this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
             pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
-                    (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            auto f = decode_inst(insn);
-            auto old_pc = pc.val;
-            pc = (this->*f)(pc, insn);
+                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+            auto inst_id = decode_inst_id(instr);
+            // pre execution stuff
+            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
+            switch(inst_id){<%instructions.eachWithIndex{instr, idx -> %>
+            case arch::traits<ARCH>::opcode_e::${instr.name}: {
+		        <%instr.fields.eachLine{%>${it}
+		        <%}%>if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            <%instr.disass.eachLine{%>${it}
+		            <%}%>
+		        }
+		        // used registers<%instr.usedVariables.each{ k,v->
+		        if(v.isArray) {%>
+		        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}0]);<% }else{ %> 
+		        auto* ${k} = reinterpret_cast<uint${nativeTypeSize(v.type.size)}_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::${k}]);
+		        <%}}%>// calculate next pc value
+		        *NEXT_PC = *PC + ${instr.length/8};
+		        // execute instruction
+		        try {
+		        <%instr.behavior.eachLine{%>${it}
+		        <%}%>} catch(...){}
+	    	}
+	    	break;<%}%>
+            default: {
+                *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
+                raise(0,  2);
+            }
+            }
+            // post execution stuff
+            process_spawn_blocks();
+            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
+            // trap check
+            if(*trap_state!=0){
+                super::core.enter_trap(*trap_state, pc.val, instr);
+            } else {
+                (*icount)++;
+                (*instret)++;
+            }
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
+            pc.val=*NEXT_PC;
             this->core.reg.PC = this->core.reg.NEXT_PC;
             this->core.reg.trap_state = this->core.reg.pending_trap;
         }
@@ -359,7 +343,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     return pc;
 }
 
-} // namespace mnrv32
+}
 
 template <>
 std::unique_ptr<vm_if> create<arch::${coreDef.name.toLowerCase()}>(arch::${coreDef.name.toLowerCase()} *core, unsigned short port, bool dump) {
diff --git a/src/vm/interp/vm_tgc_c.cpp b/src/vm/interp/vm_tgc_c.cpp
index 3b470b8..4f5f98d 100644
--- a/src/vm/interp/vm_tgc_c.cpp
+++ b/src/vm/interp/vm_tgc_c.cpp
@@ -88,7 +88,7 @@ protected:
 
     inline const char *name(size_t index){return traits::reg_aliases.at(index);}
 
-    compile_func decode_inst(code_word_t instr) ;
+    typename arch::traits<ARCH>::opcode_e decode_inst_id(code_word_t instr);
     virt_addr_t execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit) override;
 
     // some compile time constants
@@ -108,7 +108,7 @@ protected:
     struct instruction_pattern {
         uint32_t value;
         uint32_t mask;
-        compile_func opc;
+        typename arch::traits<ARCH>::opcode_e id;
     };
 
     std::array<std::vector<instruction_pattern>, 4> qlut;
@@ -193,3941 +193,102 @@ private:
         size_t length;
         uint32_t value;
         uint32_t mask;
-        compile_func op;
+        typename arch::traits<ARCH>::opcode_e op;
     };
 
     const std::array<InstructionDesriptor, 90> instr_descr = {{
          /* entries are: size, valid value, valid mask, function ptr */
-        /* instruction LUI */
-        {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
-        /* instruction AUIPC */
-        {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
-        /* instruction JAL */
-        {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
-        /* instruction JALR */
-        {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
-        /* instruction BEQ */
-        {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
-        /* instruction BNE */
-        {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
-        /* instruction BLT */
-        {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
-        /* instruction BGE */
-        {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
-        /* instruction BLTU */
-        {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
-        /* instruction BGEU */
-        {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
-        /* instruction LB */
-        {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
-        /* instruction LH */
-        {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
-        /* instruction LW */
-        {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
-        /* instruction LBU */
-        {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
-        /* instruction LHU */
-        {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
-        /* instruction SB */
-        {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
-        /* instruction SH */
-        {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
-        /* instruction SW */
-        {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
-        /* instruction ADDI */
-        {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
-        /* instruction SLTI */
-        {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
-        /* instruction SLTIU */
-        {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
-        /* instruction XORI */
-        {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
-        /* instruction ORI */
-        {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
-        /* instruction ANDI */
-        {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
-        /* instruction SLLI */
-        {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli},
-        /* instruction SRLI */
-        {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli},
-        /* instruction SRAI */
-        {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai},
-        /* instruction ADD */
-        {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
-        /* instruction SUB */
-        {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
-        /* instruction SLL */
-        {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
-        /* instruction SLT */
-        {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
-        /* instruction SLTU */
-        {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
-        /* instruction XOR */
-        {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
-        /* instruction SRL */
-        {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
-        /* instruction SRA */
-        {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
-        /* instruction OR */
-        {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
-        /* instruction AND */
-        {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
-        /* instruction FENCE */
-        {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, &this_class::__fence},
-        /* instruction ECALL */
-        {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
-        /* instruction EBREAK */
-        {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
-        /* instruction URET */
-        {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret},
-        /* instruction SRET */
-        {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret},
-        /* instruction MRET */
-        {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
-        /* instruction WFI */
-        {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
-        /* instruction DRET */
-        {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__dret},
-        /* instruction CSRRW */
-        {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
-        /* instruction CSRRS */
-        {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
-        /* instruction CSRRC */
-        {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
-        /* instruction CSRRWI */
-        {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
-        /* instruction CSRRSI */
-        {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
-        /* instruction CSRRCI */
-        {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
-        /* instruction FENCE_I */
-        {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i},
-        /* instruction MUL */
-        {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul},
-        /* instruction MULH */
-        {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh},
-        /* instruction MULHSU */
-        {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu},
-        /* instruction MULHU */
-        {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu},
-        /* instruction DIV */
-        {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div},
-        /* instruction DIVU */
-        {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu},
-        /* instruction REM */
-        {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem},
-        /* instruction REMU */
-        {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu},
-        /* instruction CADDI4SPN */
-        {16, 0b0000000000000000, 0b1110000000000011, &this_class::__caddi4spn},
-        /* instruction CLW */
-        {16, 0b0100000000000000, 0b1110000000000011, &this_class::__clw},
-        /* instruction CSW */
-        {16, 0b1100000000000000, 0b1110000000000011, &this_class::__csw},
-        /* instruction CADDI */
-        {16, 0b0000000000000001, 0b1110000000000011, &this_class::__caddi},
-        /* instruction CNOP */
-        {16, 0b0000000000000001, 0b1110111110000011, &this_class::__cnop},
-        /* instruction CJAL */
-        {16, 0b0010000000000001, 0b1110000000000011, &this_class::__cjal},
-        /* instruction CLI */
-        {16, 0b0100000000000001, 0b1110000000000011, &this_class::__cli},
-        /* instruction CLUI */
-        {16, 0b0110000000000001, 0b1110000000000011, &this_class::__clui},
-        /* instruction CADDI16SP */
-        {16, 0b0110000100000001, 0b1110111110000011, &this_class::__caddi16sp},
-        /* instruction __reserved_clui */
-        {16, 0b0110000000000001, 0b1111000001111111, &this_class::____reserved_clui},
-        /* instruction CSRLI */
-        {16, 0b1000000000000001, 0b1111110000000011, &this_class::__csrli},
-        /* instruction CSRAI */
-        {16, 0b1000010000000001, 0b1111110000000011, &this_class::__csrai},
-        /* instruction CANDI */
-        {16, 0b1000100000000001, 0b1110110000000011, &this_class::__candi},
-        /* instruction CSUB */
-        {16, 0b1000110000000001, 0b1111110001100011, &this_class::__csub},
-        /* instruction CXOR */
-        {16, 0b1000110000100001, 0b1111110001100011, &this_class::__cxor},
-        /* instruction COR */
-        {16, 0b1000110001000001, 0b1111110001100011, &this_class::__cor},
-        /* instruction CAND */
-        {16, 0b1000110001100001, 0b1111110001100011, &this_class::__cand},
-        /* instruction CJ */
-        {16, 0b1010000000000001, 0b1110000000000011, &this_class::__cj},
-        /* instruction CBEQZ */
-        {16, 0b1100000000000001, 0b1110000000000011, &this_class::__cbeqz},
-        /* instruction CBNEZ */
-        {16, 0b1110000000000001, 0b1110000000000011, &this_class::__cbnez},
-        /* instruction CSLLI */
-        {16, 0b0000000000000010, 0b1111000000000011, &this_class::__cslli},
-        /* instruction CLWSP */
-        {16, 0b0100000000000010, 0b1110000000000011, &this_class::__clwsp},
-        /* instruction CMV */
-        {16, 0b1000000000000010, 0b1111000000000011, &this_class::__cmv},
-        /* instruction CJR */
-        {16, 0b1000000000000010, 0b1111000001111111, &this_class::__cjr},
-        /* instruction __reserved_cmv */
-        {16, 0b1000000000000010, 0b1111111111111111, &this_class::____reserved_cmv},
-        /* instruction CADD */
-        {16, 0b1001000000000010, 0b1111000000000011, &this_class::__cadd},
-        /* instruction CJALR */
-        {16, 0b1001000000000010, 0b1111000001111111, &this_class::__cjalr},
-        /* instruction CEBREAK */
-        {16, 0b1001000000000010, 0b1111111111111111, &this_class::__cebreak},
-        /* instruction CSWSP */
-        {16, 0b1100000000000010, 0b1110000000000011, &this_class::__cswsp},
-        /* instruction DII */
-        {16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii},
+        {32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::LUI},
+        {32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::AUIPC},
+        {32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, arch::traits<ARCH>::opcode_e::JAL},
+        {32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::JALR},
+        {32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BEQ},
+        {32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BNE},
+        {32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BLT},
+        {32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BGE},
+        {32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BLTU},
+        {32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::BGEU},
+        {32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LB},
+        {32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LH},
+        {32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LW},
+        {32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LBU},
+        {32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::LHU},
+        {32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SB},
+        {32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SH},
+        {32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SW},
+        {32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::ADDI},
+        {32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SLTI},
+        {32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::SLTIU},
+        {32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::XORI},
+        {32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::ORI},
+        {32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::ANDI},
+        {32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLLI},
+        {32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRLI},
+        {32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRAI},
+        {32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::ADD},
+        {32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SUB},
+        {32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLL},
+        {32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLT},
+        {32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SLTU},
+        {32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::XOR},
+        {32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRL},
+        {32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::SRA},
+        {32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::OR},
+        {32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::AND},
+        {32, 0b00000000000000000000000000001111, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::FENCE},
+        {32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::ECALL},
+        {32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::EBREAK},
+        {32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::URET},
+        {32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::SRET},
+        {32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::MRET},
+        {32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::WFI},
+        {32, 0b01111011001000000000000001110011, 0b11111111111111111111111111111111, arch::traits<ARCH>::opcode_e::DRET},
+        {32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRW},
+        {32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRS},
+        {32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRC},
+        {32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRWI},
+        {32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRSI},
+        {32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::CSRRCI},
+        {32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, arch::traits<ARCH>::opcode_e::FENCE_I},
+        {32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::MUL},
+        {32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::MULH},
+        {32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::MULHSU},
+        {32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::MULHU},
+        {32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::DIV},
+        {32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::DIVU},
+        {32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::REM},
+        {32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, arch::traits<ARCH>::opcode_e::REMU},
+        {16, 0b0000000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CADDI4SPN},
+        {16, 0b0100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLW},
+        {16, 0b1100000000000000, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CSW},
+        {16, 0b0000000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CADDI},
+        {16, 0b0000000000000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::CNOP},
+        {16, 0b0010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CJAL},
+        {16, 0b0100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLI},
+        {16, 0b0110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLUI},
+        {16, 0b0110000100000001, 0b1110111110000011, arch::traits<ARCH>::opcode_e::CADDI16SP},
+        {16, 0b0110000000000001, 0b1111000001111111, arch::traits<ARCH>::opcode_e::__reserved_clui},
+        {16, 0b1000000000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::CSRLI},
+        {16, 0b1000010000000001, 0b1111110000000011, arch::traits<ARCH>::opcode_e::CSRAI},
+        {16, 0b1000100000000001, 0b1110110000000011, arch::traits<ARCH>::opcode_e::CANDI},
+        {16, 0b1000110000000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CSUB},
+        {16, 0b1000110000100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CXOR},
+        {16, 0b1000110001000001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::COR},
+        {16, 0b1000110001100001, 0b1111110001100011, arch::traits<ARCH>::opcode_e::CAND},
+        {16, 0b1010000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CJ},
+        {16, 0b1100000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CBEQZ},
+        {16, 0b1110000000000001, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CBNEZ},
+        {16, 0b0000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CSLLI},
+        {16, 0b0100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CLWSP},
+        {16, 0b1000000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CMV},
+        {16, 0b1000000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::CJR},
+        {16, 0b1000000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::__reserved_cmv},
+        {16, 0b1001000000000010, 0b1111000000000011, arch::traits<ARCH>::opcode_e::CADD},
+        {16, 0b1001000000000010, 0b1111000001111111, arch::traits<ARCH>::opcode_e::CJALR},
+        {16, 0b1001000000000010, 0b1111111111111111, arch::traits<ARCH>::opcode_e::CEBREAK},
+        {16, 0b1100000000000010, 0b1110000000000011, arch::traits<ARCH>::opcode_e::CSWSP},
+        {16, 0b0000000000000000, 0b1111111111111111, arch::traits<ARCH>::opcode_e::DII},
     }};
- 
-    /* instruction definitions */
-    /* instruction 0: LUI */
-    compile_ret_t __lui(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 0);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint32_t imm = ((bit_sub<12,20>(instr) << 12));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd != 0) *(X+rd) = (int32_t)imm; 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 0);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 1: AUIPC */
-    compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 1);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint32_t imm = ((bit_sub<12,20>(instr) << 12));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd != 0) *(X+rd) = *PC + (int32_t)imm; 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 1);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 2: JAL */
-    compile_ret_t __jal(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 2);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
-            }
-            else {
-                if(rd != 0) *(X+rd) = *PC + 4; 
-                pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 2);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 3: JALR */
-    compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 3);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            int32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 1;
-            if(new_pc % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
-            }
-            else {
-                if(rd != 0) *(X+rd) = *PC + 4; 
-                pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 3);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 4: BEQ */
-    compile_ret_t __beq(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 4);
-        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"),
-                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(*(X+rs1) == *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
-            }
-            else {
-                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 4);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 5: BNE */
-    compile_ret_t __bne(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 5);
-        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"),
-                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(*(X+rs1) != *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
-            }
-            else {
-                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 5);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 6: BLT */
-    compile_ret_t __blt(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 6);
-        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"),
-                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
-            }
-            else {
-                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 7: BGE */
-    compile_ret_t __bge(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 7);
-        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"),
-                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
-            }
-            else {
-                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 8: BLTU */
-    compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 8);
-        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"),
-                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(*(X+rs1) < *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
-            }
-            else {
-                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 8);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 9: BGEU */
-    compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 9);
-        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"),
-                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(*(X+rs1) >= *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
-                raise(0,  0);
-            }
-            else {
-                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 9);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 10: LB */
-    compile_ret_t __lb(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 10);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            int8_t res = (int8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
-            if(rd != 0) *(X+rd) = res; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 10);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 11: LH */
-    compile_ret_t __lh(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 11);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
-            int16_t res = (int16_t)readSpace2(traits::MEM, load_address);
-            if(rd != 0) *(X+rd) = res; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 11);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 12: LW */
-    compile_ret_t __lw(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 12);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
-            int32_t res = (int32_t)readSpace4(traits::MEM, load_address);
-            if(rd != 0) *(X+rd) = (uint32_t)res; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 12);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 13: LBU */
-    compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 13);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint8_t res = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
-            if(rd != 0) *(X+rd) = res; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 13);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 14: LHU */
-    compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 14);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
-            uint16_t res = (uint16_t)readSpace2(traits::MEM, load_address);
-            if(rd != 0) *(X+rd) = res; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 14);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 15: SB */
-    compile_ret_t __sb(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 15);
-        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"),
-                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        writeSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm), (int8_t)*(X+rs2));
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 15);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 16: SH */
-    compile_ret_t __sh(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 16);
-        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"),
-                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
-            writeSpace2(traits::MEM, store_address, (int16_t)*(X+rs2));
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 16);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 17: SW */
-    compile_ret_t __sw(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 17);
-        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"),
-                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
-            writeSpace4(traits::MEM, store_address, *(X+rs2));
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 17);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 18: ADDI */
-    compile_ret_t __addi(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 18);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 18);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 19: SLTI */
-    compile_ret_t __slti(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 19);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) < (int16_t)sext<12>(imm)?  1 :  0; 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 19);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 20: SLTIU */
-    compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 20);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))?  1 :  0; 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 20);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 21: XORI */
-    compile_ret_t __xori(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 21);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) ^ (int16_t)sext<12>(imm); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 21);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 22: ORI */
-    compile_ret_t __ori(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 22);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) | (int16_t)sext<12>(imm); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 22);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 23: ANDI */
-    compile_ret_t __andi(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 23);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) & (int16_t)sext<12>(imm); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 23);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 24: SLLI */
-    compile_ret_t __slli(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 24);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t shamt = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(shamt >  31) {
-            raise(0, 0);
-        }
-        else {
-            if(rd !=  0) *(X+rd) = *(X+rs1) << shamt; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 24);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 25: SRLI */
-    compile_ret_t __srli(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 25);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t shamt = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(shamt >  31) {
-            raise(0, 0);
-        }
-        else {
-            if(rd !=  0) *(X+rd) = *(X+rs1) >> shamt; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 25);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 26: SRAI */
-    compile_ret_t __srai(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 26);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t shamt = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(shamt >  31) {
-            raise(0, 0);
-        }
-        else {
-            if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) >> shamt; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 26);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 27: ADD */
-    compile_ret_t __add(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 27);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) + *(X+rs2); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 27);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 28: SUB */
-    compile_ret_t __sub(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 28);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) - *(X+rs2); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 28);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 29: SLL */
-    compile_ret_t __sll(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 29);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1)); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 29);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 30: SLT */
-    compile_ret_t __slt(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 30);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)?  1 :  0; 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 30);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 31: SLTU */
-    compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 31);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = (uint32_t)*(X+rs1) < (uint32_t)*(X+rs2)?  1 :  0; 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 31);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 32: XOR */
-    compile_ret_t __xor(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 32);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) ^ *(X+rs2); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 32);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 33: SRL */
-    compile_ret_t __srl(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 33);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 33);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 34: SRA */
-    compile_ret_t __sra(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 34);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 34);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 35: OR */
-    compile_ret_t __or(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 35);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) | *(X+rs2); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 35);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 36: AND */
-    compile_ret_t __and(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 36);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        if(rd !=  0) *(X+rd) = *(X+rs1) & *(X+rs2); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 36);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 37: FENCE */
-    compile_ret_t __fence(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 37);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t succ = ((bit_sub<20,4>(instr)));
-        uint8_t pred = ((bit_sub<24,4>(instr)));
-        uint8_t fm = ((bit_sub<28,4>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"),
-                fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        writeSpace1(traits::FENCE, traits::fence, pred << 4 | succ);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 37);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 38: ECALL */
-    compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 38);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "ecall");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        raise(0,  11);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 38);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 39: EBREAK */
-    compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 39);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "ebreak");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        raise(0,  3);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 39);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 40: URET */
-    compile_ret_t __uret(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 40);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "uret");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        leave(0);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 40);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 41: SRET */
-    compile_ret_t __sret(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 41);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "sret");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        leave(1);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 41);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 42: MRET */
-    compile_ret_t __mret(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 42);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "mret");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        leave(3);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 42);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 43: WFI */
-    compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 43);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "wfi");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        wait(1);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 43);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 44: DRET */
-    compile_ret_t __dret(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 44);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "dret");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers 
-        auto* PRIV = reinterpret_cast<uint8_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PRIV]);
-         
-        auto* DPC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::DPC]);
-        // calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(*PRIV < 4) raise(0,  2); 
-            else {
-                pc_assign(*NEXT_PC) = *DPC;
-                *PRIV &=  0x3;
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 44);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 45: CSRRW */
-    compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 45);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t csr = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"),
-                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t xrs1 = *(X+rs1);
-            if(rd != 0) {
-                uint32_t xrd = readSpace4(traits::CSR, csr);
-                writeSpace4(traits::CSR, csr, xrs1);
-                *(X+rd) = xrd;
-            }
-            else {
-                writeSpace4(traits::CSR, csr, xrs1);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 45);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 46: CSRRS */
-    compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 46);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t csr = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"),
-                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t xrd = readSpace4(traits::CSR, csr);
-            uint32_t xrs1 = *(X+rs1);
-            if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd | xrs1); 
-            if(rd != 0) *(X+rd) = xrd; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 46);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 47: CSRRC */
-    compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 47);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t csr = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"),
-                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t xrd = readSpace4(traits::CSR, csr);
-            uint32_t xrs1 = *(X+rs1);
-            if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd & ~ xrs1); 
-            if(rd != 0) *(X+rd) = xrd; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 47);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 48: CSRRWI */
-    compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 48);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t zimm = ((bit_sub<15,5>(instr)));
-        uint16_t csr = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"),
-                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t xrd = readSpace4(traits::CSR, csr);
-            writeSpace4(traits::CSR, csr, (uint32_t)zimm);
-            if(rd != 0) *(X+rd) = xrd; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 48);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 49: CSRRSI */
-    compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 49);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t zimm = ((bit_sub<15,5>(instr)));
-        uint16_t csr = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"),
-                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t xrd = readSpace4(traits::CSR, csr);
-            if(zimm != 0) writeSpace4(traits::CSR, csr, xrd | (uint32_t)zimm); 
-            if(rd != 0) *(X+rd) = xrd; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 49);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 50: CSRRCI */
-    compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 50);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t zimm = ((bit_sub<15,5>(instr)));
-        uint16_t csr = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"),
-                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            uint32_t xrd = readSpace4(traits::CSR, csr);
-            if(zimm != 0) writeSpace4(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); 
-            if(rd != 0) *(X+rd) = xrd; 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 50);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 51: FENCE_I */
-    compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 51);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint16_t imm = ((bit_sub<20,12>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
-                fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        writeSpace2(traits::FENCE, traits::fencei, imm);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 51);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 52: MUL */
-    compile_ret_t __mul(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 52);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(rd !=  0) {
-                int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
-                *(X+rd) = (uint32_t)res;
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 52);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 53: MULH */
-    compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 53);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(rd !=  0) {
-                int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
-                *(X+rd) = (uint32_t)(res >> traits::XLEN);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 53);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 54: MULHSU */
-    compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 54);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(rd !=  0) {
-                int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
-                *(X+rd) = (uint32_t)(res >> traits::XLEN);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 54);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 55: MULHU */
-    compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 55);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(rd !=  0) {
-                uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
-                *(X+rd) = (uint32_t)(res >> traits::XLEN);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 55);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 56: DIV */
-    compile_ret_t __div(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 56);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(rd !=  0) {
-                if(*(X+rs2) != 0) {
-                    uint32_t MMIN =  1 << (traits::XLEN - 1);
-                    if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) = MMIN; 
-                    else *(X+rd) = (int32_t)*(X+rs1) / (int32_t)*(X+rs2);
-                }
-                else *(X+rd) = - 1;
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 56);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 57: DIVU */
-    compile_ret_t __divu(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 57);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(rd !=  0) {
-                if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) / *(X+rs2); 
-                else *(X+rd) = - 1;
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 57);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 58: REM */
-    compile_ret_t __rem(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 58);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(rd !=  0) {
-                if(*(X+rs2) != 0) {
-                    uint32_t MMIN =  1 << (traits::XLEN - 1);
-                    if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) =  0; 
-                    else *(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2);
-                }
-                else *(X+rd) = *(X+rs1);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 58);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 59: REMU */
-    compile_ret_t __remu(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 59);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        uint8_t rs1 = ((bit_sub<15,5>(instr)));
-        uint8_t rs2 = ((bit_sub<20,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 4;
-        // execute instruction
-        try {
-        {
-            if(rd !=  0) {
-                if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) % *(X+rs2); 
-                else *(X+rd) = *(X+rs1);
-            }
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 59);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 60: CADDI4SPN */
-    compile_ret_t __caddi4spn(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 60);
-        uint8_t rd = ((bit_sub<2,3>(instr)));
-        uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        if(imm) *(X+(rd + 8)) = *(X+2) + imm; 
-        else raise(0,  2);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 60);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 61: CLW */
-    compile_ret_t __clw(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 61);
-        uint8_t rd = ((bit_sub<2,3>(instr)));
-        uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
-        uint8_t rs1 = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "clw"),
-                fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            uint32_t load_address = *(X+(rs1 + 8)) + uimm;
-            *(X+(rd + 8)) = (int32_t)readSpace4(traits::MEM, load_address);
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 61);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 62: CSW */
-    compile_ret_t __csw(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 62);
-        uint8_t rs2 = ((bit_sub<2,3>(instr)));
-        uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
-        uint8_t rs1 = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "csw"),
-                fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            uint32_t load_address = *(X+(rs1 + 8)) + uimm;
-            writeSpace4(traits::MEM, load_address, *(X+(rs2 + 8)));
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 62);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 63: CADDI */
-    compile_ret_t __caddi(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 63);
-        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "caddi"),
-                fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        *(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 63);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 64: CNOP */
-    compile_ret_t __cnop(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 64);
-        uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "cnop");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 64);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 65: CJAL */
-    compile_ret_t __cjal(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 65);
-        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cjal"),
-                fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            *(X+1) = *PC + 2;
-            pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm);
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 66: CLI */
-    compile_ret_t __cli(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 66);
-        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "cli"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            if(rd !=  0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm); 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 66);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 67: CLUI */
-    compile_ret_t __clui(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 67);
-        uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "clui"),
-                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            if(imm ==  0) raise(0,  2); 
-            if(rd !=  0) *(X+rd) = (int32_t)sext<18>(imm); 
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 67);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 68: CADDI16SP */
-    compile_ret_t __caddi16sp(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 68);
-        uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "caddi16sp"),
-                fmt::arg("nzimm", nzimm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        if(nzimm) *(X+2) = *(X+2) + (int16_t)sext<10>(nzimm); 
-        else raise(0,  2);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 68);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 69: __reserved_clui */
-    compile_ret_t ____reserved_clui(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 69);
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "__reserved_clui");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        raise(0,  2);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 69);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 70: CSRLI */
-    compile_ret_t __csrli(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 70);
-        uint8_t shamt = ((bit_sub<2,5>(instr)));
-        uint8_t rs1 = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrli"),
-                fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            uint32_t rs1_idx = rs1 + 8;
-            *(X+rs1_idx) = *(X+rs1_idx) >> shamt;
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 70);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 71: CSRAI */
-    compile_ret_t __csrai(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 71);
-        uint8_t shamt = ((bit_sub<2,5>(instr)));
-        uint8_t rs1 = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrai"),
-                fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        if(shamt) {
-            uint32_t rs1_idx = rs1 + 8;
-            *(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >> shamt;
-        }
-        else if(traits::XLEN == 128) {
-            uint32_t rs1_idx = rs1 + 8;
-            *(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >>  64;
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 71);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 72: CANDI */
-    compile_ret_t __candi(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 72);
-        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
-        uint8_t rs1 = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "candi"),
-                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            uint32_t rs1_idx = rs1 +  8;
-            *(X+rs1_idx) = *(X+rs1_idx) & (int8_t)sext<6>(imm);
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 72);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 73: CSUB */
-    compile_ret_t __csub(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 73);
-        uint8_t rs2 = ((bit_sub<2,3>(instr)));
-        uint8_t rd = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "csub"),
-                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            uint32_t rd_idx = rd +  8;
-            *(X+rd_idx) = *(X+rd_idx) - *(X+(rs2 +  8));
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 73);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 74: CXOR */
-    compile_ret_t __cxor(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 74);
-        uint8_t rs2 = ((bit_sub<2,3>(instr)));
-        uint8_t rd = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cxor"),
-                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            uint32_t rd_idx = rd +  8;
-            *(X+rd_idx) = *(X+rd_idx) ^ *(X+(rs2 +  8));
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 74);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 75: COR */
-    compile_ret_t __cor(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 75);
-        uint8_t rs2 = ((bit_sub<2,3>(instr)));
-        uint8_t rd = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cor"),
-                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            uint32_t rd_idx = rd +  8;
-            *(X+rd_idx) = *(X+rd_idx) | *(X+(rs2 +  8));
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 75);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 76: CAND */
-    compile_ret_t __cand(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 76);
-        uint8_t rs2 = ((bit_sub<2,3>(instr)));
-        uint8_t rd = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cand"),
-                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            uint32_t rd_idx = rd +  8;
-            *(X+rd_idx) = *(X+rd_idx) & *(X+(rs2 +  8));
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 76);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 77: CJ */
-    compile_ret_t __cj(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 77);
-        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cj"),
-                fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 77);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 78: CBEQZ */
-    compile_ret_t __cbeqz(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 78);
-        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
-        uint8_t rs1 = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbeqz"),
-                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        if(*(X+(rs1 + 8)) == 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 78);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 79: CBNEZ */
-    compile_ret_t __cbnez(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 79);
-        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
-        uint8_t rs1 = ((bit_sub<7,3>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbnez"),
-                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        if(*(X+(rs1 + 8)) != 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 79);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 80: CSLLI */
-    compile_ret_t __cslli(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 80);
-        uint8_t nzuimm = ((bit_sub<2,5>(instr)));
-        uint8_t rs1 = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "cslli"),
-                fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        if(nzuimm) *(X+rs1) = *(X+rs1) << nzuimm; 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 80);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 81: CLWSP */
-    compile_ret_t __clwsp(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 81);
-        uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "clwsp"),
-                fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        if(rd) {
-            uint32_t offs = *(X+2) + uimm;
-            *(X+rd) = (int32_t)readSpace4(traits::MEM, offs);
-        }
-        else raise(0, 2);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 81);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 82: CMV */
-    compile_ret_t __cmv(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 82);
-        uint8_t rs2 = ((bit_sub<2,5>(instr)));
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cmv"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        if(rd != 0) *(X+rd) = *(X+rs2); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 82);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 83: CJR */
-    compile_ret_t __cjr(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 83);
-        uint8_t rs1 = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjr"),
-                fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        if(rs1) pc_assign(*NEXT_PC) = *(X+rs1) & ~ 0x1; 
-        else raise(0, 2);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 83);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 84: __reserved_cmv */
-    compile_ret_t ____reserved_cmv(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 84);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "__reserved_cmv");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        raise(0, 2);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 84);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 85: CADD */
-    compile_ret_t __cadd(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 85);
-        uint8_t rs2 = ((bit_sub<2,5>(instr)));
-        uint8_t rd = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cadd"),
-                fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        if(rd != 0) *(X+rd) = *(X+rd) + *(X+rs2); 
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 85);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 86: CJALR */
-    compile_ret_t __cjalr(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 86);
-        uint8_t rs1 = ((bit_sub<7,5>(instr)));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjalr"),
-                fmt::arg("rs1", name(rs1)));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            int32_t new_pc = *(X+rs1);
-            *(X+1) = *PC + 2;
-            pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 86);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 87: CEBREAK */
-    compile_ret_t __cebreak(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 87);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "cebreak");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        raise(0,  3);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 87);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 88: CSWSP */
-    compile_ret_t __cswsp(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 88);
-        uint8_t rs2 = ((bit_sub<2,5>(instr)));
-        uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            auto mnemonic = fmt::format(
-                "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "cswsp"),
-                fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
-            this->core.disass_output(pc.val, mnemonic);
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers
-        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        {
-            uint32_t offs = *(X+2) + uimm;
-            writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2));
-        }
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 88);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /* instruction 89: DII */
-    compile_ret_t __dii(virt_addr_t& pc, code_word_t instr){
-        // pre execution stuff
-        if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, 89);
-        if(this->disass_enabled){
-            /* generate console output when executing the command */
-            this->core.disass_output(pc.val, "dii");
-            
-        }
-        auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // used registers// calculate next pc value
-        *NEXT_PC = *PC + 2;
-        // execute instruction
-        try {
-        raise(0,  2);
-        } catch(...){}
-        // post execution stuff
-        process_spawn_blocks();
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 89);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        } else {
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]))++;
-            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]))++;
-        }
-        (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
-        pc.val=*NEXT_PC;
-        return pc;
-    }
-    
-    /****************************************************************************
-     * end opcode definitions
-     ****************************************************************************/
-    compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
-        this->do_sync(PRE_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
-        uint32_t* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
-        *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
-        raise(0,  2);
-        // post execution stuff
-        if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, static_cast<unsigned>(arch::traits<ARCH>::opcode_e::MAX_OPCODE));
-        auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
-        // trap check
-        if(*trap_state!=0){
-            super::core.enter_trap(*trap_state, pc.val, instr);
-        }
-        pc.val=*NEXT_PC;
-        return pc;
-    }
 
     //static constexpr typename traits::addr_t upper_bits = ~traits::PGMASK;
     iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
@@ -4167,6 +328,7 @@ constexpr size_t bit_count(uint32_t u) {
 template <typename ARCH>
 vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
 : vm_base<ARCH>(core, core_id, cluster_id) {
+    unsigned id=0;
     for (auto instr : instr_descr) {
         auto quadrant = instr.value & 0x3;
         qlut[quadrant].push_back(instruction_pattern{instr.value, instr.mask, instr.op});
@@ -4187,31 +349,2073 @@ inline bool is_jump_to_self_enabled(finish_cond_e cond){
 }
 
 template <typename ARCH>
-typename vm_impl<ARCH>::compile_func vm_impl<ARCH>::decode_inst(code_word_t instr){
+typename arch::traits<ARCH>::opcode_e vm_impl<ARCH>::decode_inst_id(code_word_t instr){
     for(auto& e: qlut[instr&0x3]){
-        if(!((instr&e.mask) ^ e.value )) return e.opc;
+        if(!((instr&e.mask) ^ e.value )) return e.id;
     }
-    return &this_class::illegal_intruction;
+    return arch::traits<ARCH>::opcode_e::MAX_OPCODE;
 }
 
 template <typename ARCH>
 typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e cond, virt_addr_t start, uint64_t icount_limit){
     // we fetch at max 4 byte, alignment is 2
-    code_word_t insn = 0;
-    auto *const data = (uint8_t *)&insn;
+    code_word_t instr = 0;
+    auto *const data = (uint8_t *)&instr;
     auto pc=start;
+
+    auto* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
+    auto* NEXT_PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::NEXT_PC]);
+    auto* trap_state = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::TRAP_STATE]);
+    auto* icount = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::ICOUNT]);
+    auto* instret = reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::INSTRET]);
+
     while(!this->core.should_stop() &&
             !(is_count_limit_enabled(cond) && this->core.get_icount() >= icount_limit)){
-        auto res = fetch_ins(pc, data);
-        if(res!=iss::Ok){
+        if(fetch_ins(pc, data)!=iss::Ok){
             this->do_sync(POST_SYNC, std::numeric_limits<unsigned>::max());
             pc.val = super::core.enter_trap(std::numeric_limits<uint64_t>::max(), pc.val, 0);
         } else {
             if (is_jump_to_self_enabled(cond) &&
-                    (insn == 0x0000006f || (insn&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
-            auto f = decode_inst(insn);
-            auto old_pc = pc.val;
-            pc = (this->*f)(pc, insn);
+                    (instr == 0x0000006f || (instr&0xffff)==0xa001)) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
+            auto inst_id = decode_inst_id(instr);
+            // pre execution stuff
+            if(this->sync_exec && PRE_SYNC) this->do_sync(PRE_SYNC, static_cast<unsigned>(inst_id));
+            switch(inst_id){
+            case arch::traits<ARCH>::opcode_e::LUI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint32_t imm = ((bit_sub<12,20>(instr) << 12));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd != 0) *(X+rd) = (int32_t)imm; 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::AUIPC: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint32_t imm = ((bit_sub<12,20>(instr) << 12));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd != 0) *(X+rd) = *PC + (int32_t)imm; 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::JAL: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint32_t imm = ((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(imm % traits::INSTR_ALIGNMENT) {
+		                raise(0,  0);
+		            }
+		            else {
+		                if(rd != 0) *(X+rd) = *PC + 4; 
+		                pc_assign(*NEXT_PC) = *PC + (int32_t)sext<21>(imm);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::JALR: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            int32_t new_pc = (*(X+rs1) + (int16_t)sext<12>(imm)) & ~ 1;
+		            if(new_pc % traits::INSTR_ALIGNMENT) {
+		                raise(0,  0);
+		            }
+		            else {
+		                if(rd != 0) *(X+rd) = *PC + 4; 
+		                pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::BEQ: {
+		        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"),
+		                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(*(X+rs1) == *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+		                raise(0,  0);
+		            }
+		            else {
+		                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::BNE: {
+		        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"),
+		                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(*(X+rs1) != *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+		                raise(0,  0);
+		            }
+		            else {
+		                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::BLT: {
+		        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"),
+		                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if((int32_t)*(X+rs1) < (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+		                raise(0,  0);
+		            }
+		            else {
+		                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::BGE: {
+		        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"),
+		                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if((int32_t)*(X+rs1) >= (int32_t)*(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+		                raise(0,  0);
+		            }
+		            else {
+		                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::BLTU: {
+		        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"),
+		                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(*(X+rs1) < *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+		                raise(0,  0);
+		            }
+		            else {
+		                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::BGEU: {
+		        uint16_t imm = ((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"),
+		                fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(*(X+rs1) >= *(X+rs2)) if(imm % traits::INSTR_ALIGNMENT) {
+		                raise(0,  0);
+		            }
+		            else {
+		                pc_assign(*NEXT_PC) = *PC + (int16_t)sext<13>(imm);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::LB: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            int8_t res = (int8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
+		            if(rd != 0) *(X+rd) = res; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::LH: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+		            int16_t res = (int16_t)readSpace2(traits::MEM, load_address);
+		            if(rd != 0) *(X+rd) = res; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::LW: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+		            int32_t res = (int32_t)readSpace4(traits::MEM, load_address);
+		            if(rd != 0) *(X+rd) = (uint32_t)res; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::LBU: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint8_t res = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm));
+		            if(rd != 0) *(X+rd) = res; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::LHU: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t load_address = *(X+rs1) + (int16_t)sext<12>(imm);
+		            uint16_t res = (uint16_t)readSpace2(traits::MEM, load_address);
+		            if(rd != 0) *(X+rd) = res; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SB: {
+		        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"),
+		                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        writeSpace1(traits::MEM, *(X+rs1) + (int16_t)sext<12>(imm), (int8_t)*(X+rs2));
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SH: {
+		        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"),
+		                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
+		            writeSpace2(traits::MEM, store_address, (int16_t)*(X+rs2));
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SW: {
+		        uint16_t imm = ((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"),
+		                fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t store_address = *(X+rs1) + (int16_t)sext<12>(imm);
+		            writeSpace4(traits::MEM, store_address, *(X+rs2));
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::ADDI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) + (int16_t)sext<12>(imm); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SLTI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) < (int16_t)sext<12>(imm)?  1 :  0; 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SLTIU: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = (*(X+rs1) < (uint32_t)((int16_t)sext<12>(imm)))?  1 :  0; 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::XORI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) ^ (int16_t)sext<12>(imm); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::ORI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) | (int16_t)sext<12>(imm); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::ANDI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) & (int16_t)sext<12>(imm); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SLLI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t shamt = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(shamt >  31) {
+		            raise(0, 0);
+		        }
+		        else {
+		            if(rd !=  0) *(X+rd) = *(X+rs1) << shamt; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SRLI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t shamt = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(shamt >  31) {
+		            raise(0, 0);
+		        }
+		        else {
+		            if(rd !=  0) *(X+rd) = *(X+rs1) >> shamt; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SRAI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t shamt = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(shamt >  31) {
+		            raise(0, 0);
+		        }
+		        else {
+		            if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) >> shamt; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::ADD: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) + *(X+rs2); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SUB: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) - *(X+rs2); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SLL: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1)); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SLT: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) < (int32_t)*(X+rs2)?  1 :  0; 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SLTU: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = (uint32_t)*(X+rs1) < (uint32_t)*(X+rs2)?  1 :  0; 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::XOR: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) ^ *(X+rs2); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SRL: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SRA: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = (int32_t)*(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1)); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::OR: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) | *(X+rs2); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::AND: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        if(rd !=  0) *(X+rd) = *(X+rs1) & *(X+rs2); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::FENCE: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t succ = ((bit_sub<20,4>(instr)));
+		        uint8_t pred = ((bit_sub<24,4>(instr)));
+		        uint8_t fm = ((bit_sub<28,4>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {pred}, {succ} ({fm} , {rs1}, {rd})", fmt::arg("mnemonic", "fence"),
+		                fmt::arg("pred", pred), fmt::arg("succ", succ), fmt::arg("fm", fm), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        writeSpace1(traits::FENCE, traits::fence, pred << 4 | succ);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::ECALL: {
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "ecall");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        raise(0,  11);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::EBREAK: {
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "ebreak");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        raise(0,  3);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::URET: {
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "uret");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        leave(0);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::SRET: {
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "sret");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        leave(1);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::MRET: {
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "mret");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        leave(3);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::WFI: {
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "wfi");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        wait(1);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::DRET: {
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "dret");
+		            
+		        }
+		        // used registers 
+		        auto* PRIV = reinterpret_cast<uint8_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PRIV]);
+		         
+		        auto* DPC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::DPC]);
+		        // calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(*PRIV < 4) raise(0,  2); 
+		            else {
+		                pc_assign(*NEXT_PC) = *DPC;
+		                *PRIV &=  0x3;
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSRRW: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t csr = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"),
+		                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t xrs1 = *(X+rs1);
+		            if(rd != 0) {
+		                uint32_t xrd = readSpace4(traits::CSR, csr);
+		                writeSpace4(traits::CSR, csr, xrs1);
+		                *(X+rd) = xrd;
+		            }
+		            else {
+		                writeSpace4(traits::CSR, csr, xrs1);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSRRS: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t csr = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"),
+		                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t xrd = readSpace4(traits::CSR, csr);
+		            uint32_t xrs1 = *(X+rs1);
+		            if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd | xrs1); 
+		            if(rd != 0) *(X+rd) = xrd; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSRRC: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t csr = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"),
+		                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t xrd = readSpace4(traits::CSR, csr);
+		            uint32_t xrs1 = *(X+rs1);
+		            if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd & ~ xrs1); 
+		            if(rd != 0) *(X+rd) = xrd; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSRRWI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t zimm = ((bit_sub<15,5>(instr)));
+		        uint16_t csr = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"),
+		                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t xrd = readSpace4(traits::CSR, csr);
+		            writeSpace4(traits::CSR, csr, (uint32_t)zimm);
+		            if(rd != 0) *(X+rd) = xrd; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSRRSI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t zimm = ((bit_sub<15,5>(instr)));
+		        uint16_t csr = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"),
+		                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t xrd = readSpace4(traits::CSR, csr);
+		            if(zimm != 0) writeSpace4(traits::CSR, csr, xrd | (uint32_t)zimm); 
+		            if(rd != 0) *(X+rd) = xrd; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSRRCI: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t zimm = ((bit_sub<15,5>(instr)));
+		        uint16_t csr = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"),
+		                fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t xrd = readSpace4(traits::CSR, csr);
+		            if(zimm != 0) writeSpace4(traits::CSR, csr, xrd & ~ ((uint32_t)zimm)); 
+		            if(rd != 0) *(X+rd) = xrd; 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::FENCE_I: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint16_t imm = ((bit_sub<20,12>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
+		                fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        writeSpace2(traits::FENCE, traits::fencei, imm);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::MUL: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(rd !=  0) {
+		                int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
+		                *(X+rd) = (uint32_t)res;
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::MULH: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(rd !=  0) {
+		                int64_t res = (int64_t)(int32_t)*(X+rs1) * (int64_t)(int32_t)*(X+rs2);
+		                *(X+rd) = (uint32_t)(res >> traits::XLEN);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::MULHSU: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(rd !=  0) {
+		                int64_t res = (int64_t)(int32_t)*(X+rs1) * (uint64_t)*(X+rs2);
+		                *(X+rd) = (uint32_t)(res >> traits::XLEN);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::MULHU: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(rd !=  0) {
+		                uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
+		                *(X+rd) = (uint32_t)(res >> traits::XLEN);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::DIV: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(rd !=  0) {
+		                if(*(X+rs2) != 0) {
+		                    uint32_t MMIN =  1 << (traits::XLEN - 1);
+		                    if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) = MMIN; 
+		                    else *(X+rd) = (int32_t)*(X+rs1) / (int32_t)*(X+rs2);
+		                }
+		                else *(X+rd) = - 1;
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::DIVU: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(rd !=  0) {
+		                if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) / *(X+rs2); 
+		                else *(X+rd) = - 1;
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::REM: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(rd !=  0) {
+		                if(*(X+rs2) != 0) {
+		                    uint32_t MMIN =  1 << (traits::XLEN - 1);
+		                    if(*(X+rs1) == MMIN && (int32_t)*(X+rs2) == - 1) *(X+rd) =  0; 
+		                    else *(X+rd) = (int32_t)*(X+rs1) % (int32_t)*(X+rs2);
+		                }
+		                else *(X+rd) = *(X+rs1);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::REMU: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<15,5>(instr)));
+		        uint8_t rs2 = ((bit_sub<20,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 4;
+		        // execute instruction
+		        try {
+		        {
+		            if(rd !=  0) {
+		                if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) % *(X+rs2); 
+		                else *(X+rd) = *(X+rs1);
+		            }
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CADDI4SPN: {
+		        uint8_t rd = ((bit_sub<2,3>(instr)));
+		        uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        if(imm) *(X+(rd + 8)) = *(X+2) + imm; 
+		        else raise(0,  2);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CLW: {
+		        uint8_t rd = ((bit_sub<2,3>(instr)));
+		        uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
+		        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "clw"),
+		                fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t load_address = *(X+(rs1 + 8)) + uimm;
+		            *(X+(rd + 8)) = (int32_t)readSpace4(traits::MEM, load_address);
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSW: {
+		        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+		        uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
+		        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "csw"),
+		                fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t load_address = *(X+(rs1 + 8)) + uimm;
+		            writeSpace4(traits::MEM, load_address, *(X+(rs2 + 8)));
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CADDI: {
+		        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+		        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "caddi"),
+		                fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        *(X+rs1) = *(X+rs1) + (int8_t)sext<6>(imm);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CNOP: {
+		        uint8_t nzimm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "cnop");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CJAL: {
+		        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cjal"),
+		                fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            *(X+1) = *PC + 2;
+		            pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm);
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CLI: {
+		        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "cli"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            if(rd !=  0) *(X+rd) = (uint32_t)(int32_t)sext<6>(imm); 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CLUI: {
+		        uint32_t imm = ((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "clui"),
+		                fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            if(imm ==  0) raise(0,  2); 
+		            if(rd !=  0) *(X+rd) = (int32_t)sext<18>(imm); 
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CADDI16SP: {
+		        uint16_t nzimm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {nzimm:#05x}", fmt::arg("mnemonic", "caddi16sp"),
+		                fmt::arg("nzimm", nzimm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        if(nzimm) *(X+2) = *(X+2) + (int16_t)sext<10>(nzimm); 
+		        else raise(0,  2);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::__reserved_clui: {
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "__reserved_clui");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        raise(0,  2);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSRLI: {
+		        uint8_t shamt = ((bit_sub<2,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrli"),
+		                fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t rs1_idx = rs1 + 8;
+		            *(X+rs1_idx) = *(X+rs1_idx) >> shamt;
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSRAI: {
+		        uint8_t shamt = ((bit_sub<2,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrai"),
+		                fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        if(shamt) {
+		            uint32_t rs1_idx = rs1 + 8;
+		            *(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >> shamt;
+		        }
+		        else if(traits::XLEN == 128) {
+		            uint32_t rs1_idx = rs1 + 8;
+		            *(X+rs1_idx) = ((int32_t)*(X+rs1_idx)) >>  64;
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CANDI: {
+		        uint8_t imm = ((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
+		        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "candi"),
+		                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t rs1_idx = rs1 +  8;
+		            *(X+rs1_idx) = *(X+rs1_idx) & (int8_t)sext<6>(imm);
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSUB: {
+		        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+		        uint8_t rd = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "csub"),
+		                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t rd_idx = rd +  8;
+		            *(X+rd_idx) = *(X+rd_idx) - *(X+(rs2 +  8));
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CXOR: {
+		        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+		        uint8_t rd = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cxor"),
+		                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t rd_idx = rd +  8;
+		            *(X+rd_idx) = *(X+rd_idx) ^ *(X+(rs2 +  8));
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::COR: {
+		        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+		        uint8_t rd = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cor"),
+		                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t rd_idx = rd +  8;
+		            *(X+rd_idx) = *(X+rd_idx) | *(X+(rs2 +  8));
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CAND: {
+		        uint8_t rs2 = ((bit_sub<2,3>(instr)));
+		        uint8_t rd = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cand"),
+		                fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t rd_idx = rd +  8;
+		            *(X+rd_idx) = *(X+rd_idx) & *(X+(rs2 +  8));
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CJ: {
+		        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cj"),
+		                fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        pc_assign(*NEXT_PC) = *PC + (int16_t)sext<12>(imm);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CBEQZ: {
+		        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
+		        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbeqz"),
+		                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        if(*(X+(rs1 + 8)) == 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CBNEZ: {
+		        uint16_t imm = ((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
+		        uint8_t rs1 = ((bit_sub<7,3>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbnez"),
+		                fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        if(*(X+(rs1 + 8)) != 0) pc_assign(*NEXT_PC) = *PC + (int16_t)sext<9>(imm); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSLLI: {
+		        uint8_t nzuimm = ((bit_sub<2,5>(instr)));
+		        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}, {nzuimm}", fmt::arg("mnemonic", "cslli"),
+		                fmt::arg("rs1", name(rs1)), fmt::arg("nzuimm", nzuimm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        if(nzuimm) *(X+rs1) = *(X+rs1) << nzuimm; 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CLWSP: {
+		        uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "clwsp"),
+		                fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        if(rd) {
+		            uint32_t offs = *(X+2) + uimm;
+		            *(X+rd) = (int32_t)readSpace4(traits::MEM, offs);
+		        }
+		        else raise(0, 2);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CMV: {
+		        uint8_t rs2 = ((bit_sub<2,5>(instr)));
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cmv"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        if(rd != 0) *(X+rd) = *(X+rs2); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CJR: {
+		        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjr"),
+		                fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        if(rs1) pc_assign(*NEXT_PC) = *(X+rs1) & ~ 0x1; 
+		        else raise(0, 2);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::__reserved_cmv: {
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "__reserved_cmv");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        raise(0, 2);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CADD: {
+		        uint8_t rs2 = ((bit_sub<2,5>(instr)));
+		        uint8_t rd = ((bit_sub<7,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cadd"),
+		                fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        if(rd != 0) *(X+rd) = *(X+rd) + *(X+rs2); 
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CJALR: {
+		        uint8_t rs1 = ((bit_sub<7,5>(instr)));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjalr"),
+		                fmt::arg("rs1", name(rs1)));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            int32_t new_pc = *(X+rs1);
+		            *(X+1) = *PC + 2;
+		            pc_assign(*NEXT_PC) = new_pc & ~ 0x1;
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CEBREAK: {
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "cebreak");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        raise(0,  3);
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::CSWSP: {
+		        uint8_t rs2 = ((bit_sub<2,5>(instr)));
+		        uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            auto mnemonic = fmt::format(
+		                "{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "cswsp"),
+		                fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
+		            this->core.disass_output(pc.val, mnemonic);
+		            
+		        }
+		        // used registers
+		        auto* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        {
+		            uint32_t offs = *(X+2) + uimm;
+		            writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2));
+		        }
+		        } catch(...){}
+	    	}
+	    	break;
+            case arch::traits<ARCH>::opcode_e::DII: {
+		        if(this->disass_enabled){
+		            /* generate console output when executing the command */
+		            this->core.disass_output(pc.val, "dii");
+		            
+		        }
+		        // used registers// calculate next pc value
+		        *NEXT_PC = *PC + 2;
+		        // execute instruction
+		        try {
+		        raise(0,  2);
+		        } catch(...){}
+	    	}
+	    	break;
+            default: {
+                *NEXT_PC = *PC + ((instr & 3) == 3 ? 4 : 2);
+                raise(0,  2);
+            }
+            }
+            // post execution stuff
+            process_spawn_blocks();
+            if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
+            // trap check
+            if(*trap_state!=0){
+                super::core.enter_trap(*trap_state, pc.val, instr);
+            } else {
+                (*icount)++;
+                (*instret)++;
+            }
+            (*reinterpret_cast<uint64_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::CYCLE]))++;
+            pc.val=*NEXT_PC;
             this->core.reg.PC = this->core.reg.NEXT_PC;
             this->core.reg.trap_state = this->core.reg.pending_trap;
         }
@@ -4219,7 +2423,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
     return pc;
 }
 
-} // namespace mnrv32
+}
 
 template <>
 std::unique_ptr<vm_if> create<arch::tgc_c>(arch::tgc_c *core, unsigned short port, bool dump) {