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DBT-RISE-TGC
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fixes templates

This commit is contained in:
Eyck Jentzsch 2024-06-14 19:54:33 +02:00
parent 551822916c
commit 3fd51cc68c
3 changed files with 159 additions and 205 deletions
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4
gen_input/templates/interp/CORENAME.cpp.gtl
View File

@ -368,7 +368,7 @@ volatile std::array<bool, 2> dummy = {
auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port); if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){ if(init_data){
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data); auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb); cpu->set_semihosting_callback(*cb);
} }
return {cpu_ptr{cpu}, vm_ptr{vm}}; return {cpu_ptr{cpu}, vm_ptr{vm}};
@ -378,7 +378,7 @@ volatile std::array<bool, 2> dummy = {
auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false); auto vm = new interp::${coreDef.name.toLowerCase()}::vm_impl<arch::${coreDef.name.toLowerCase()}>(*cpu, false);
if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port); if (port != 0) debugger::server<debugger::gdb_session>::run_server(vm, port);
if(init_data){ if(init_data){
auto* cb = reinterpret_cast<std::function<void(arch_if*, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t, arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t)>*>(init_data); auto* cb = reinterpret_cast<semihosting_cb_t<arch::traits<arch::${coreDef.name.toLowerCase()}>::reg_t>*>(init_data);
cpu->set_semihosting_callback(*cb); cpu->set_semihosting_callback(*cb);
} }
return {cpu_ptr{cpu}, vm_ptr{vm}}; return {cpu_ptr{cpu}, vm_ptr{vm}};

46
src/iss/arch/tgc5c.h
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@ -76,53 +76,7 @@ template <> struct traits<tgc5c> {
static constexpr std::array<const uint32_t, 43> reg_byte_offsets{ static constexpr std::array<const uint32_t, 43> reg_byte_offsets{
{0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}}; {0,4,8,12,16,20,24,28,32,36,40,44,48,52,56,60,64,68,72,76,80,84,88,92,96,100,104,108,112,116,120,124,128,132,136,137,141,145,149,157,165,173,177}};
/*
For easy lookup:
X0 (zero): 0x0000
X1 (ra) : 0x0004
X2 (sp) : 0x0008
X3 (gp) : 0x000c
X4 (tp) : 0x0010
X5 (t0) : 0x0014
X6 (t1) : 0x0018
X7 (t2) : 0x001c
X8 (s0/fp): 0x0020
X9 (s1) : 0x0024
X10 (a0) : 0x0028
X11 (a1) : 0x002c
X12 (a2) : 0x0030
X13 (a3) : 0x0034
X14 (a4) : 0x0038
X15 (a5) : 0x003c
X16 (a6) : 0x0040
X17 (a7) : 0x0044
X18 (s2) : 0x0048
X19 (s3) : 0x004c
X20 (s4) : 0x0050
X21 (s5) : 0x0054
X22 (s6) : 0x0058
X23 (s7) : 0x005c
X24 (s8) : 0x0060
X25 (s9) : 0x0064
X26 (s10) : 0x0068
X27 (s11) : 0x006c
X28 (t3) : 0x0070
X29 (t4) : 0x0074
X30 (t5) : 0x0078
X31 (t6) : 0x007c
PC : 0x0080
NEXT_PC : 0x0084
PRIV : 0x0085
DPC : 0x0089
trap_state : 0x008d
pending_trap : 0x0091
icount : 0x0095
cycle : 0x009d
instret : 0x00a5
instruction : 0x00ad
last_branch : 0x00b1
*/
static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1); static const uint64_t addr_mask = (reg_t(1) << (XLEN - 1)) | ((reg_t(1) << (XLEN - 1)) - 1);
enum sreg_flag_e { FLAGS }; enum sreg_flag_e { FLAGS };

18
src/vm/interp/vm_tgc5c.cpp
View File

@ -459,7 +459,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 4 )); *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(4 ));
} }
*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)sext<21>(imm) )); *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int32_t)sext<21>(imm) ));
this->core.reg.last_branch = 1; this->core.reg.last_branch = 1;
@ -495,7 +495,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 4 )); *(X+rd) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(4 ));
} }
*NEXT_PC = new_pc; *NEXT_PC = new_pc;
this->core.reg.last_branch = 1; this->core.reg.last_branch = 1;
@ -1256,7 +1256,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1) << ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 ))); *(X+rd) = *(X+rs1) << ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )));
} }
} }
} }
@ -1364,7 +1364,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = *(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 ))); *(X+rd) = *(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 )));
} }
} }
} }
@ -1391,7 +1391,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
if(rd != 0) { if(rd != 0) {
*(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)( 1 )))); *(X+rd) = (uint32_t)((int32_t)*(X+rs1) >> ((uint64_t)(*(X+rs2) ) & ((uint64_t)(traits::XLEN ) - (uint64_t)(1 ))));
} }
} }
} }
@ -2136,7 +2136,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
*NEXT_PC = *PC + 2; *NEXT_PC = *PC + 2;
// execute instruction // execute instruction
{ {
*(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 2 )); *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(2 ));
*NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) )); *NEXT_PC = (uint32_t)((uint64_t)(*PC ) + (uint64_t)((int16_t)sext<12>(imm) ));
this->core.reg.last_branch = 1; this->core.reg.last_branch = 1;
} }
@ -2525,7 +2525,7 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
// execute instruction // execute instruction
{ {
if(rs1 && rs1 < traits::RFS) { if(rs1 && rs1 < traits::RFS) {
*NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & (uint32_t)(~ 0x1 ); *NEXT_PC = *(X+(uint32_t)(rs1 ) % traits::RFS) & (uint32_t)(~ 1 );
this->core.reg.last_branch = 1; this->core.reg.last_branch = 1;
} }
else { else {
@ -2592,8 +2592,8 @@ typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(finish_cond_e co
} }
else { else {
uint32_t new_pc = *(X+rs1); uint32_t new_pc = *(X+rs1);
*(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)( 2 )); *(X+1) = (uint32_t)((uint64_t)(*PC ) + (uint64_t)(2 ));
*NEXT_PC = new_pc & (uint32_t)(~ 0x1 ); *NEXT_PC = new_pc & (uint32_t)(~ 1 );
this->core.reg.last_branch = 1; this->core.reg.last_branch = 1;
} }
} }