fixes CLIC mtvt register behavior
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ad1cbedf00
commit
3f7ce41b9d
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@ -312,6 +312,7 @@ protected:
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iss::status write_epc(unsigned addr, reg_t val);
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iss::status write_epc(unsigned addr, reg_t val);
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iss::status write_intstatus(unsigned addr, reg_t val);
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iss::status write_intstatus(unsigned addr, reg_t val);
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iss::status write_intthresh(unsigned addr, reg_t val);
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iss::status write_intthresh(unsigned addr, reg_t val);
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iss::status write_xtvt(unsigned addr, reg_t val);
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iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
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iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
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iss::status read_dcsr_reg(unsigned addr, reg_t &val);
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iss::status read_dcsr_reg(unsigned addr, reg_t &val);
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iss::status write_dcsr_reg(unsigned addr, reg_t val);
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iss::status write_dcsr_reg(unsigned addr, reg_t val);
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@ -413,7 +414,7 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
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csr_wr_cb[mimpid] = &this_class::write_null;
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csr_wr_cb[mimpid] = &this_class::write_null;
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if(FEAT & FEAT_CLIC) {
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if(FEAT & FEAT_CLIC) {
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csr_rd_cb[mtvt] = &this_class::read_csr_reg;
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csr_rd_cb[mtvt] = &this_class::read_csr_reg;
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csr_wr_cb[mtvt] = &this_class::write_csr_reg;
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csr_wr_cb[mtvt] = &this_class::write_xtvt;
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csr_rd_cb[mxnti] = &this_class::read_csr_reg;
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csr_rd_cb[mxnti] = &this_class::read_csr_reg;
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csr_wr_cb[mxnti] = &this_class::write_csr_reg;
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csr_wr_cb[mxnti] = &this_class::write_csr_reg;
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csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
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csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
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@ -943,6 +944,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val
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return iss::Ok;
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return iss::Ok;
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}
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}
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template<typename BASE, features_e FEAT>
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iss::status riscv_hart_mu_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
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csr[addr]= val & ~0x3fULL;
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT>
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template <typename BASE, features_e FEAT>
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iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
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iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
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switch (paddr.val) {
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switch (paddr.val) {
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@ -329,6 +329,7 @@ protected:
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iss::status write_epc(unsigned addr, reg_t val);
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iss::status write_epc(unsigned addr, reg_t val);
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iss::status write_intstatus(unsigned addr, reg_t val);
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iss::status write_intstatus(unsigned addr, reg_t val);
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iss::status write_intthresh(unsigned addr, reg_t val);
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iss::status write_intthresh(unsigned addr, reg_t val);
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iss::status write_xtvt(unsigned addr, reg_t val);
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iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
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iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
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iss::status read_dcsr_reg(unsigned addr, reg_t &val);
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iss::status read_dcsr_reg(unsigned addr, reg_t &val);
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iss::status write_dcsr_reg(unsigned addr, reg_t val);
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iss::status write_dcsr_reg(unsigned addr, reg_t val);
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@ -460,7 +461,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
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}
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}
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if(FEAT & FEAT_CLIC) {
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if(FEAT & FEAT_CLIC) {
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csr_rd_cb[mtvt] = &this_class::read_csr_reg;
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csr_rd_cb[mtvt] = &this_class::read_csr_reg;
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csr_wr_cb[mtvt] = &this_class::write_csr_reg;
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csr_wr_cb[mtvt] = &this_class::write_xtvt;
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csr_rd_cb[mxnti] = &this_class::read_csr_reg;
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csr_rd_cb[mxnti] = &this_class::read_csr_reg;
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csr_wr_cb[mxnti] = &this_class::write_csr_reg;
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csr_wr_cb[mxnti] = &this_class::write_csr_reg;
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csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
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csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
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@ -1109,6 +1110,12 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t va
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return iss::Ok;
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return iss::Ok;
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}
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}
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template<typename BASE, features_e FEAT>
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iss::status riscv_hart_mu_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
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csr[addr]= val & ~0x3fULL;
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT>
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template <typename BASE, features_e FEAT>
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iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
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iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
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switch (paddr.val) {
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switch (paddr.val) {
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