From 3f7ce41b9d2d21973950293e0573b585adb966cf Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 11 Mar 2023 14:03:03 +0100
Subject: [PATCH] fixes CLIC mtvt register behavior

---
 src/iss/arch/riscv_hart_m_p.h  | 9 ++++++++-
 src/iss/arch/riscv_hart_mu_p.h | 9 ++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h
index b8f63ca..c57263c 100644
--- a/src/iss/arch/riscv_hart_m_p.h
+++ b/src/iss/arch/riscv_hart_m_p.h
@@ -312,6 +312,7 @@ protected:
     iss::status write_epc(unsigned addr, reg_t val);
     iss::status write_intstatus(unsigned addr, reg_t val);
     iss::status write_intthresh(unsigned addr, reg_t val);
+    iss::status write_xtvt(unsigned addr, reg_t val);
     iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
     iss::status read_dcsr_reg(unsigned addr, reg_t &val);
     iss::status write_dcsr_reg(unsigned addr, reg_t val);
@@ -413,7 +414,7 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
     csr_wr_cb[mimpid] = &this_class::write_null;
     if(FEAT & FEAT_CLIC) {
         csr_rd_cb[mtvt] = &this_class::read_csr_reg;
-        csr_wr_cb[mtvt] = &this_class::write_csr_reg;
+        csr_wr_cb[mtvt] = &this_class::write_xtvt;
         csr_rd_cb[mxnti] = &this_class::read_csr_reg;
         csr_wr_cb[mxnti] = &this_class::write_csr_reg;
         csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
@@ -943,6 +944,12 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t val
     return iss::Ok;
 }
 
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
+    csr[addr]= val & ~0x3fULL;
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_m_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
     switch (paddr.val) {
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index 7ed92ea..d4032c3 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -329,6 +329,7 @@ protected:
     iss::status write_epc(unsigned addr, reg_t val);
     iss::status write_intstatus(unsigned addr, reg_t val);
     iss::status write_intthresh(unsigned addr, reg_t val);
+    iss::status write_xtvt(unsigned addr, reg_t val);
     iss::status write_dcsr_dcsr(unsigned addr, reg_t val);
     iss::status read_dcsr_reg(unsigned addr, reg_t &val);
     iss::status write_dcsr_reg(unsigned addr, reg_t val);
@@ -460,7 +461,7 @@ riscv_hart_mu_p<BASE, FEAT>::riscv_hart_mu_p(feature_config cfg)
     }
     if(FEAT & FEAT_CLIC) {
         csr_rd_cb[mtvt] = &this_class::read_csr_reg;
-        csr_wr_cb[mtvt] = &this_class::write_csr_reg;
+        csr_wr_cb[mtvt] = &this_class::write_xtvt;
         csr_rd_cb[mxnti] = &this_class::read_csr_reg;
         csr_wr_cb[mxnti] = &this_class::write_csr_reg;
         csr_rd_cb[mintstatus] = &this_class::read_csr_reg;
@@ -1109,6 +1110,12 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write_intthresh(unsigned addr, reg_t va
     return iss::Ok;
 }
 
+template<typename BASE, features_e FEAT>
+iss::status riscv_hart_mu_p<BASE, FEAT>::write_xtvt(unsigned addr, reg_t val) {
+    csr[addr]= val & ~0x3fULL;
+    return iss::Ok;
+}
+
 template <typename BASE, features_e FEAT>
 iss::status riscv_hart_mu_p<BASE, FEAT>::read_mem(phys_addr_t paddr, unsigned length, uint8_t *const data) {
     switch (paddr.val) {