DBT-RISE
/
DBT-RISE-TGC
11
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

adds reformat bc of verilog literals

This commit is contained in:
Eyck-Alexander Jentzsch 2024-05-18 21:00:54 +02:00
parent a27850f841
commit 3cc8bd0854
2 changed files with 353 additions and 356 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
src/vm/llvm/vm_tgc5c.cpp
View File

@ -4292,10 +4292,9 @@ private:
this->gen_set_pc(pc, traits::NEXT_PC);
/*generate behavior*/
if(rs1&&rs1<static_cast<uint32_t>(traits::RFS)){ auto addr_mask =this->gen_const(32,(uint32_t)- 2);
auto PC_val_v = this->builder.CreateAnd(
if(rs1&&rs1<static_cast<uint32_t>(traits::RFS)){ auto PC_val_v = this->builder.CreateAnd(
this->gen_reg_load(rs1%static_cast<uint32_t>(traits::RFS)+ traits::X0, 0),
addr_mask)
this->gen_const(32,~ 1))
;
this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false);
this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);
@ -4411,14 +4410,13 @@ private:
this->gen_raise_trap(0, 2);
}
else{
auto addr_mask =this->gen_const(32,(uint32_t)- 2);
auto new_pc =this->gen_reg_load(rs1+ traits::X0, 0);
this->builder.CreateStore(
this->gen_const(32,(uint32_t)(PC+2)),
get_reg_ptr(1 + traits::X0), false);
auto PC_val_v = this->builder.CreateAnd(
new_pc,
addr_mask)
this->gen_const(32,~ 1))
;
this->builder.CreateStore(PC_val_v, get_reg_ptr(traits::NEXT_PC), false);
this->builder.CreateStore(this->gen_const(32,2U), get_reg_ptr(traits::LAST_BRANCH), false);

9
src/vm/tcc/vm_tgc5c.cpp
View File

@ -2171,7 +2171,7 @@ private:
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();
tu.write_mem(traits::FENCE, static_cast<uint32_t>(traits:: fencei), tu.constant(imm,16));
auto returnValue = std::make_tuple(CONT);
auto returnValue = std::make_tuple(FLUSH);
tu.close_scope();
gen_trap_check(tu);
@ -3303,10 +3303,9 @@ private:
pc=pc+ 2;
gen_set_pc(tu, pc, traits::NEXT_PC);
tu.open_scope();
if(rs1&&rs1<static_cast<uint32_t>(traits:: RFS)) {
auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
if(rs1&&rs1<static_cast<uint32_t>(traits:: RFS)){ auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
tu.load(rs1%static_cast<uint32_t>(traits:: RFS)+ traits::X0, 0),
tu.constant(~ 0x1,8)),32);
tu.constant(~ 1,32)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
}
@ -3406,7 +3405,7 @@ private:
tu.constant((uint32_t)(PC+2),32));
auto PC_val_v = tu.assignment("PC_val", tu.bitwise_and(
new_pc,
tu.constant(~ 0x1,8)),32);
tu.constant(~ 1,32)),32);
tu.store(traits::NEXT_PC, PC_val_v);
tu.store(traits::LAST_BRANCH, tu.constant(2U, 2));
}