DBT-RISE/DBT-RISE-TGC
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fixes build system and typo in wt_cache

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Eyck Jentzsch
2023-05-13 16:57:01 +02:00
parent 6789cf4c32
commit 32848ec396
4 changed files with 17 additions and 8 deletions
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4
src/iss/arch/wt_cache.h
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@ -120,7 +120,7 @@ iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uin
if((a.val&io_addr_mask) != io_address) {
auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
auto tag_addr=a.val>>util::ilog2(line_sz);
auto& set = (a.access==access_type::FETCH?icache_ptr:dcache_ptr)->sets[set_addr];
auto& set = (is_fetch(a.access)?icache_ptr:dcache_ptr)->sets[set_addr];
for(auto& cl: set.ways) {
if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
auto start_addr = a.val&(line_sz-1);
@ -156,7 +156,7 @@ iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, co
if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
auto start_addr = a.val&(line_sz-1);
for(auto i = 0U; i<l; ++i)
cl.data[start_addr+1] = d[i];
cl.data[start_addr+i] = d[i];
break;
}
}