From 32848ec3969d02a40c43961e9302b8b7b49e915c Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Sat, 13 May 2023 16:57:01 +0200
Subject: [PATCH] fixes build system and typo in wt_cache

---
 CMakeLists.txt                 | 11 ++++++++++-
 src/iss/arch/riscv_hart_mu_p.h |  8 ++++----
 src/iss/arch/wt_cache.h        |  4 ++--
 src/sysc/core_complex.cpp      |  2 +-
 4 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/CMakeLists.txt b/CMakeLists.txt
index e135fb7..1625ee5 100644
--- a/CMakeLists.txt
+++ b/CMakeLists.txt
@@ -131,7 +131,16 @@ project(tgc-sim)
 find_package(Boost COMPONENTS program_options thread REQUIRED)
 
 add_executable(${PROJECT_NAME} src/main.cpp)
-FILE(GLOB TGC_SOURCES  ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp) 
+if(TARGET ${CORE_NAME}_cpp)
+    list(APPEND TGC_SOURCES ${${CORE_NAME}_OUTPUT_FILES})
+else()
+    FILE(GLOB TGC_SOURCES
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/iss/arch/*.cpp
+        ${CMAKE_CURRENT_SOURCE_DIR}/src-gen/vm/interp/vm_*.cpp
+    )
+    list(APPEND TGC_SOURCES ${GEN_SOURCES})
+endif()
+
 foreach(F IN LISTS TGC_SOURCES)
     string(REGEX REPLACE  ".*/([^/]*)\.cpp"  "\\1" CORE_NAME_LC ${F})
     string(TOUPPER ${CORE_NAME_LC} CORE_NAME)
diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h
index f8ab194..719276d 100644
--- a/src/iss/arch/riscv_hart_mu_p.h
+++ b/src/iss/arch/riscv_hart_mu_p.h
@@ -803,7 +803,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
 #ifndef NDEBUG
     if (access && iss::access_type::DEBUG) {
         LOG(TRACEALL) << "debug read of " << length << " bytes @addr 0x" << std::hex << addr;
-    } else if(access && iss::access_type::FETCH){
+    } else if(is_fetch(access)){
         LOG(TRACEALL) << "fetch of " << length << " bytes  @addr 0x" << std::hex << addr;
     } else {
         LOG(TRACE) << "read of " << length << " bytes  @addr 0x" << std::hex << addr;
@@ -835,7 +835,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
                 }
                 auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
                 auto res = iss::Err;
-                if(access != access_type::FETCH && memfn_range.size()){
+                if(!is_fetch(access) && memfn_range.size()){
                     auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
                         return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
                     });
@@ -922,7 +922,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                     return iss::Err;
                 }
             }
-            if (unlikely((access && iss::access_type::FETCH) && (addr & 0x1) == 1)) {
+            if (unlikely(is_fetch(access) && (addr & 0x1) == 1)) {
                 fault_data = addr;
                 if (access && iss::access_type::DEBUG) throw trap_access(0, addr);
                 this->trap_state = (1UL << 31); // issue trap 0
@@ -936,7 +936,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
                 }
                 auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr});
                 auto res = iss::Err;
-                if(access != access_type::FETCH && memfn_range.size()){
+                if(!is_fetch(access) && memfn_range.size()){
                     auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
                         return std::get<0>(a)<=phys_addr.val && (std::get<0>(a)+std::get<1>(a))>phys_addr.val;
                     });
diff --git a/src/iss/arch/wt_cache.h b/src/iss/arch/wt_cache.h
index d5acf3c..2b3835b 100644
--- a/src/iss/arch/wt_cache.h
+++ b/src/iss/arch/wt_cache.h
@@ -120,7 +120,7 @@ iss::status iss::arch::wt_cache<BASE>::read_cache(phys_addr_t a, unsigned l, uin
     if((a.val&io_addr_mask) != io_address) {
         auto set_addr=(a.val&(size-1))>>util::ilog2(line_sz*ways);
         auto tag_addr=a.val>>util::ilog2(line_sz);
-        auto& set = (a.access==access_type::FETCH?icache_ptr:dcache_ptr)->sets[set_addr];
+        auto& set = (is_fetch(a.access)?icache_ptr:dcache_ptr)->sets[set_addr];
         for(auto& cl: set.ways) {
             if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
                 auto start_addr = a.val&(line_sz-1);
@@ -156,7 +156,7 @@ iss::status iss::arch::wt_cache<BASE>::write_cache(phys_addr_t a, unsigned l, co
             if(cl.st==cache::state::VALID && cl.tag_addr==tag_addr) {
                 auto start_addr = a.val&(line_sz-1);
                 for(auto i = 0U; i<l; ++i)
-                    cl.data[start_addr+1] = d[i];
+                    cl.data[start_addr+i] = d[i];
                 break;
             }
         }
diff --git a/src/sysc/core_complex.cpp b/src/sysc/core_complex.cpp
index 8b8d75c..f3a7ae4 100644
--- a/src/sysc/core_complex.cpp
+++ b/src/sysc/core_complex.cpp
@@ -129,7 +129,7 @@ public:
         if (addr.access && access_type::DEBUG)
             return owner->read_mem_dbg(addr.val, length, data) ? Ok : Err;
         else {
-            return owner->read_mem(addr.val, length, data, addr.access && access_type::FETCH) ? Ok : Err;
+            return owner->read_mem(addr.val, length, data, is_fetch(addr.access)) ? Ok : Err;
         }
     }