DBT-RISE/DBT-RISE-TGC
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update description to latest CoreDSL2

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eyck committed 2021-02-15 11:35:56 +00:00
1 parent 34bb8e62ae
commit 3261055871
2 files changed
+3 -3
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gen_input/CoreDSL-Instruction-Set-Description
+1 -1
Submodule gen_input/CoreDSL-Instruction-Set-Description updated: 998444fba8...919a3c8611.
gen_input/TGFS.core_desc
+2 -2
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@@ -3,7 +3,7 @@ import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc" import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGF_B provides RV32I { Core TGF_B provides RV32I {
constants { architectural_state {
unsigned XLEN=32; unsigned XLEN=32;
unsigned PCLEN=32; unsigned PCLEN=32;
// definitions for the architecture wrapper // definitions for the architecture wrapper
@@ -15,7 +15,7 @@ Core TGF_B provides RV32I {
} }
Core TGF_C provides RV32I, RV32M, RV32IC { Core TGF_C provides RV32I, RV32M, RV32IC {
constants { architectural_state {
unsigned XLEN=32; unsigned XLEN=32;
unsigned PCLEN=32; unsigned PCLEN=32;
// definitions for the architecture wrapper // definitions for the architecture wrapper