From 3261055871c646a4b47594db242a8634f1148511 Mon Sep 17 00:00:00 2001
From: Eyck Jentzsch <eyck@minres.com>
Date: Mon, 15 Feb 2021 11:35:56 +0000
Subject: [PATCH] update description to latest CoreDSL2

---
 gen_input/CoreDSL-Instruction-Set-Description | 2 +-
 gen_input/TGFS.core_desc                      | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/gen_input/CoreDSL-Instruction-Set-Description b/gen_input/CoreDSL-Instruction-Set-Description
index 998444f..919a3c8 160000
--- a/gen_input/CoreDSL-Instruction-Set-Description
+++ b/gen_input/CoreDSL-Instruction-Set-Description
@@ -1 +1 @@
-Subproject commit 998444fba8e9273fda6a4d9c89303b62129500f2
+Subproject commit 919a3c861112aa1205950d9f03055adfc801f741
diff --git a/gen_input/TGFS.core_desc b/gen_input/TGFS.core_desc
index c0aeb2b..7e04c19 100644
--- a/gen_input/TGFS.core_desc
+++ b/gen_input/TGFS.core_desc
@@ -3,7 +3,7 @@ import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
 import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
 
 Core TGF_B provides RV32I {
-	constants {
+	architectural_state {
         unsigned XLEN=32;
         unsigned PCLEN=32;
         // definitions for the architecture wrapper
@@ -15,7 +15,7 @@ Core TGF_B provides RV32I {
 }
 
 Core TGF_C provides RV32I, RV32M, RV32IC {
-    constants {
+    architectural_state {
         unsigned XLEN=32;
         unsigned PCLEN=32;
         // definitions for the architecture wrapper