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fix clic_cfg access scheme

This commit is contained in:
Eyck Jentzsch 2021-11-17 07:59:02 +01:00
parent 965929d1eb
commit 309758b994
1 changed files with 1 additions and 1 deletions
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2
incl/iss/arch/riscv_hart_mu_p.h
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@ -1222,7 +1222,7 @@ template<typename BASE, features_e FEAT>
iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) { iss::status riscv_hart_mu_p<BASE, FEAT>::write_clic(uint64_t addr, unsigned length, const uint8_t *const data) {
if(addr==clic_base_addr) { // cliccfg if(addr==clic_base_addr) { // cliccfg
clic_cfg_reg = *data; clic_cfg_reg = *data;
clic_cfg_reg&= 0x7f; clic_cfg_reg&= 0x7e;
// } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo // } else if(addr>=(clic_base_addr+4) && (addr+length)<=(clic_base_addr+4)){ // clicinfo
// write_uint32(addr, clic_info_reg, data, length); // write_uint32(addr, clic_info_reg, data, length);
} else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0xC0)){ // clicinttrig } else if(addr>=(clic_base_addr+0x40) && (addr+length)<=(clic_base_addr+0xC0)){ // clicinttrig