DBT-RISE/DBT-RISE-TGC
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[WIP] add next increment for TCC

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This commit is contained in:
Eyck Jentzsch
2020-04-17 19:23:43 +02:00
parent ae1c0b99fe
commit 264053a8d6
6 changed files with 517 additions and 509 deletions
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4
incl/iss/arch/mnrv32.h
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@ -182,6 +182,8 @@ struct mnrv32: public arch_if {
inline bool should_stop() { return interrupt_sim; }
inline uint64_t stop_code() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<mnrv32>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
@ -238,7 +240,7 @@ protected:
std::array<address_type, 4> addr_mode;
bool interrupt_sim=false;
uint64_t interrupt_sim=0;
uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){}

6
incl/iss/arch/riscv_hart_msu_vp.h
View File

@ -1082,7 +1082,10 @@ iss::status riscv_hart_msu_vp<BASE>::write_mem(phys_addr_t paddr, unsigned lengt
LOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar
<< "), stopping simulation";
}
throw(iss::simulation_stopped(hostvar));
this->reg.trap_state=std::numeric_limits<uint32_t>::max();
this->interrupt_sim=hostvar;
break;
//throw(iss::simulation_stopped(hostvar));
case 0x0101: {
char c = static_cast<char>(hostvar & 0xff);
if (c == '\n' || c == 0) {
@ -1313,6 +1316,7 @@ template <typename BASE> uint64_t riscv_hart_msu_vp<BASE>::enter_trap(uint64_t f
this->reg.trap_state = 0;
std::array<char, 32> buffer;
sprintf(buffer.data(), "0x%016lx", addr);
if((flags&0xffffffff) != 0xffffffff)
CLOG(INFO, disass) << (trap_id ? "Interrupt" : "Trap") << " with cause '"
<< (trap_id ? irq_str[cause] : trap_str[cause]) << "' (" << trap_id << ")"
<< " at address " << buffer.data() << " occurred, changing privilege level from "