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removes v2p function

This commit is contained in:
Eyck Jentzsch 2023-08-04 13:08:10 +02:00
parent e151416f58
commit 20e920338c
10 changed files with 45 additions and 58 deletions
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4
gen_input/templates/CORENAME.cpp.gtl
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@ -70,7 +70,7 @@ uint8_t *${coreDef.name.toLowerCase()}::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg); return reinterpret_cast<uint8_t*>(&reg);
} }
${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &pc) { ${coreDef.name.toLowerCase()}::phys_addr_t ${coreDef.name.toLowerCase()}::virt2phys(const iss::addr_t &addr) {
return phys_addr_t(pc); // change logical address to physical address return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
} }

8
gen_input/templates/CORENAME.h.gtl
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@ -137,14 +137,6 @@ struct ${coreDef.name.toLowerCase()}: public arch_if {
inline uint64_t stop_code() { return interrupt_sim; } inline uint64_t stop_code() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<${coreDef.name.toLowerCase()}>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<${coreDef.name.toLowerCase()}>::addr_mask);
} else
return virt2phys(addr);
}
virtual phys_addr_t virt2phys(const iss::addr_t& addr); virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }

17
src/iss/arch/riscv_hart_m_p.h
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@ -666,7 +666,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
fault_data=addr; fault_data=addr;
return iss::Err; return iss::Err;
} }
auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr}); phys_addr_t phys_addr{access, space, addr};
auto res = iss::Err; auto res = iss::Err;
if(access != access_type::FETCH && memfn_range.size()){ if(access != access_type::FETCH && memfn_range.size()){
auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){ auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
@ -759,7 +759,7 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
fault_data=addr; fault_data=addr;
return iss::Err; return iss::Err;
} }
auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr}); phys_addr_t phys_addr{access, space, addr};
auto res = iss::Err; auto res = iss::Err;
if(access != access_type::FETCH && memfn_range.size()){ if(access != access_type::FETCH && memfn_range.size()){
auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){ auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
@ -784,9 +784,8 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
return iss::Err; return iss::Err;
} }
phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr}); if ((addr + length) > mem.size()) return iss::Err;
if ((paddr.val + length) > mem.size()) return iss::Err; switch (addr) {
switch (paddr.val) {
case 0x10013000: // UART0 base, TXFIFO reg case 0x10013000: // UART0 base, TXFIFO reg
case 0x10023000: // UART1 base, TXFIFO reg case 0x10023000: // UART1 base, TXFIFO reg
uart_buf << (char)data[0]; uart_buf << (char)data[0];
@ -798,16 +797,16 @@ iss::status riscv_hart_m_p<BASE, FEAT>::write(const address_type type, const acc
} }
return iss::Ok; return iss::Ok;
case 0x10008000: { // HFROSC base, hfrosccfg reg case 0x10008000: { // HFROSC base, hfrosccfg reg
auto &p = mem(paddr.val / mem.page_size); auto &p = mem(addr / mem.page_size);
auto offs = paddr.val & mem.page_addr_mask; auto offs = addr & mem.page_addr_mask;
std::copy(data, data + length, p.data() + offs); std::copy(data, data + length, p.data() + offs);
auto &x = *(p.data() + offs + 3); auto &x = *(p.data() + offs + 3);
if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1 if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
return iss::Ok; return iss::Ok;
} }
case 0x10008008: { // HFROSC base, pllcfg reg case 0x10008008: { // HFROSC base, pllcfg reg
auto &p = mem(paddr.val / mem.page_size); auto &p = mem(addr / mem.page_size);
auto offs = paddr.val & mem.page_addr_mask; auto offs = addr & mem.page_addr_mask;
std::copy(data, data + length, p.data() + offs); std::copy(data, data + length, p.data() + offs);
auto &x = *(p.data() + offs + 3); auto &x = *(p.data() + offs + 3);
x |= 0x80; // set pll lock upon writing x |= 0x80; // set pll lock upon writing

11
src/iss/arch/riscv_hart_msu_vp.h
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@ -430,6 +430,7 @@ template <typename BASE>
riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp() riscv_hart_msu_vp<BASE>::riscv_hart_msu_vp()
: state() : state()
, instr_if(*this) { , instr_if(*this) {
this->_has_mmu = true;
// reset values // reset values
csr[misa] = traits<BASE>::MISA_VAL; csr[misa] = traits<BASE>::MISA_VAL;
csr[mvendorid] = 0x669; csr[mvendorid] = 0x669;
@ -632,9 +633,7 @@ iss::status riscv_hart_msu_vp<BASE>::read(const address_type type, const access_
return res; return res;
} }
} }
auto res = type==iss::address_type::PHYSICAL? auto res = read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
read_mem( BASE::v2p(phys_addr_t{access, space, addr}), length, data):
read_mem( BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
if (unlikely(res != iss::Ok)){ if (unlikely(res != iss::Ok)){
this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault this->reg.trap_state = (1 << 31) | (5 << 16); // issue trap 5 (load access fault
fault_data=addr; fault_data=addr;
@ -719,6 +718,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
this->reg.trap_state = (1 << 31); // issue trap 0 this->reg.trap_state = (1 << 31); // issue trap 0
return iss::Err; return iss::Err;
} }
phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
try { try {
if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary if (unlikely((addr & ~PGMASK) != ((addr + length - 1) & ~PGMASK))) { // we may cross a page boundary
vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp); vm_info vm = hart_state_type::decode_vm_info(this->reg.PRIV, state.satp);
@ -731,9 +731,7 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
return res; return res;
} }
} }
auto res = type==iss::address_type::PHYSICAL? auto res = write_mem(paddr, length, data);
write_mem(phys_addr_t{access, space, addr}, length, data):
write_mem(BASE::v2p(iss::addr_t{access, type, space, addr}), length, data);
if (unlikely(res != iss::Ok)) { if (unlikely(res != iss::Ok)) {
this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault) this->reg.trap_state = (1UL << 31) | (7UL << 16); // issue trap 7 (Store/AMO access fault)
fault_data=addr; fault_data=addr;
@ -745,7 +743,6 @@ iss::status riscv_hart_msu_vp<BASE>::write(const address_type type, const access
return iss::Err; return iss::Err;
} }
phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr});
if ((paddr.val + length) > mem.size()) return iss::Err; if ((paddr.val + length) > mem.size()) return iss::Err;
switch (paddr.val) { switch (paddr.val) {
case 0x10013000: // UART0 base, TXFIFO reg case 0x10013000: // UART0 base, TXFIFO reg

19
src/iss/arch/riscv_hart_mu_p.h
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@ -834,7 +834,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::read(const address_type type, const acc
fault_data=addr; fault_data=addr;
return iss::Err; return iss::Err;
} }
auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr}); phys_addr_t phys_addr{access, space, addr};
auto res = iss::Err; auto res = iss::Err;
if(!is_fetch(access) && memfn_range.size()){ if(!is_fetch(access) && memfn_range.size()){
auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){ auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
@ -935,7 +935,7 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
fault_data=addr; fault_data=addr;
return iss::Err; return iss::Err;
} }
auto phys_addr = type==iss::address_type::PHYSICAL?phys_addr_t{access, space, addr}:BASE::v2p(iss::addr_t{access, type, space, addr}); phys_addr_t phys_addr{access, space, addr};
auto res = iss::Err; auto res = iss::Err;
if(!is_fetch(access) && memfn_range.size()){ if(!is_fetch(access) && memfn_range.size()){
auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){ auto it = std::find_if(std::begin(memfn_range), std::end(memfn_range), [phys_addr](std::tuple<uint64_t, uint64_t> const& a){
@ -960,30 +960,29 @@ iss::status riscv_hart_mu_p<BASE, FEAT>::write(const address_type type, const ac
return iss::Err; return iss::Err;
} }
phys_addr_t paddr = BASE::v2p(iss::addr_t{access, type, space, addr}); if ((addr + length) > mem.size()) return iss::Err;
if ((paddr.val + length) > mem.size()) return iss::Err; switch (addr) {
switch (paddr.val) {
case 0x10013000: // UART0 base, TXFIFO reg case 0x10013000: // UART0 base, TXFIFO reg
case 0x10023000: // UART1 base, TXFIFO reg case 0x10023000: // UART1 base, TXFIFO reg
uart_buf << (char)data[0]; uart_buf << (char)data[0];
if (((char)data[0]) == '\n' || data[0] == 0) { if (((char)data[0]) == '\n' || data[0] == 0) {
// LOG(INFO)<<"UART"<<((paddr.val>>16)&0x3)<<" send // LOG(INFO)<<"UART"<<((addr>>16)&0x3)<<" send
// '"<<uart_buf.str()<<"'"; // '"<<uart_buf.str()<<"'";
std::cout << uart_buf.str(); std::cout << uart_buf.str();
uart_buf.str(""); uart_buf.str("");
} }
return iss::Ok; return iss::Ok;
case 0x10008000: { // HFROSC base, hfrosccfg reg case 0x10008000: { // HFROSC base, hfrosccfg reg
auto &p = mem(paddr.val / mem.page_size); auto &p = mem(addr / mem.page_size);
auto offs = paddr.val & mem.page_addr_mask; auto offs = addr & mem.page_addr_mask;
std::copy(data, data + length, p.data() + offs); std::copy(data, data + length, p.data() + offs);
auto &x = *(p.data() + offs + 3); auto &x = *(p.data() + offs + 3);
if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1 if (x & 0x40) x |= 0x80; // hfroscrdy = 1 if hfroscen==1
return iss::Ok; return iss::Ok;
} }
case 0x10008008: { // HFROSC base, pllcfg reg case 0x10008008: { // HFROSC base, pllcfg reg
auto &p = mem(paddr.val / mem.page_size); auto &p = mem(addr / mem.page_size);
auto offs = paddr.val & mem.page_addr_mask; auto offs = addr & mem.page_addr_mask;
std::copy(data, data + length, p.data() + offs); std::copy(data, data + length, p.data() + offs);
auto &x = *(p.data() + offs + 3); auto &x = *(p.data() + offs + 3);
x |= 0x80; // set pll lock upon writing x |= 0x80; // set pll lock upon writing

4
src/iss/arch/tgc_c.cpp
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@ -63,7 +63,7 @@ uint8_t *tgc_c::get_regs_base_ptr() {
return reinterpret_cast<uint8_t*>(&reg); return reinterpret_cast<uint8_t*>(&reg);
} }
tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &pc) { tgc_c::phys_addr_t tgc_c::virt2phys(const iss::addr_t &addr) {
return phys_addr_t(pc); // change logical address to physical address return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
} }

9
src/iss/arch/tgc_c.h
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@ -195,14 +195,6 @@ struct tgc_c: public arch_if {
inline uint64_t stop_code() { return interrupt_sim; } inline uint64_t stop_code() { return interrupt_sim; }
inline phys_addr_t v2p(const iss::addr_t& addr){
if (addr.space != traits<tgc_c>::MEM || addr.type == iss::address_type::PHYSICAL ||
addr_mode[static_cast<uint16_t>(addr.access)&0x3]==address_type::PHYSICAL) {
return phys_addr_t(addr.access, addr.space, addr.val&traits<tgc_c>::addr_mask);
} else
return virt2phys(addr);
}
virtual phys_addr_t virt2phys(const iss::addr_t& addr); virtual phys_addr_t virt2phys(const iss::addr_t& addr);
virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; } virtual iss::sync_type needed_sync() const { return iss::NO_SYNC; }
@ -262,7 +254,6 @@ struct tgc_c: public arch_if {
uint32_t get_fcsr(){return 0;} uint32_t get_fcsr(){return 0;}
void set_fcsr(uint32_t val){} void set_fcsr(uint32_t val){}
}; };
} }

15
src/vm/interp/vm_tgc_c.cpp
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@ -259,15 +259,22 @@ private:
}}; }};
iss::status fetch_ins(virt_addr_t pc, uint8_t * data){ iss::status fetch_ins(virt_addr_t pc, uint8_t * data){
auto phys_pc = this->core.v2p(pc); if(this->core.has_mmu()) {
//TODO: re-add page handling auto phys_pc = this->core.virt2phys(pc);
// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary // if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
// if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err; // if (this->core.read(phys_pc, 2, data) != iss::Ok) return iss::Err;
// if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction // if ((data[0] & 0x3) == 0x3) // this is a 32bit instruction
// if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) return iss::Err; // if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok)
// return iss::Err;
// } else { // } else {
if (this->core.read(phys_pc, 4, data) != iss::Ok) return iss::Err; if (this->core.read(phys_pc, 4, data) != iss::Ok)
return iss::Err;
// } // }
} else {
if (this->core.read(phys_addr_t(pc.access, pc.space, pc.val), 4, data) != iss::Ok)
return iss::Err;
}
return iss::Ok; return iss::Ok;
} }
void populate_decoding_tree(decoding_tree_node* root){ void populate_decoding_tree(decoding_tree_node* root){

3
src/vm/llvm/vm_tgc_c.cpp
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@ -4085,7 +4085,8 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
// const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK; // const typename traits<ARCH>::addr_t upper_bits = ~traits<ARCH>::PGMASK;
phys_addr_t paddr(pc); phys_addr_t paddr(pc);
auto *const data = (uint8_t *)&insn; auto *const data = (uint8_t *)&insn;
paddr = this->core.v2p(pc); if(this->core.has_mmu())
paddr = this->core.virt2phys(pc);
//TODO: re-add page handling //TODO: re-add page handling
// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary // if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
// auto res = this->core.read(paddr, 2, data); // auto res = this->core.read(paddr, 2, data);

3
src/vm/tcc/vm_tgc_c.cpp
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@ -3174,7 +3174,8 @@ vm_impl<ARCH>::gen_single_inst_behavior(virt_addr_t &pc, unsigned int &inst_cnt,
enum {TRAP_ID=1<<16}; enum {TRAP_ID=1<<16};
code_word_t instr = 0; code_word_t instr = 0;
phys_addr_t paddr(pc); phys_addr_t paddr(pc);
paddr = this->core.v2p(pc); if(this->core.has_mmu())
paddr = this->core.virt2phys(pc);
//TODO: re-add page handling //TODO: re-add page handling
// if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary // if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
// auto res = this->core.read(paddr, 2, data); // auto res = this->core.read(paddr, 2, data);