DBT-RISE/DBT-RISE-TGC
12
0
Fork 0
Code Issues 1 Pull Requests 1 Projects Releases Wiki Activity

adds WT cache functionality as mixin

Browse Source
This commit is contained in:
Eyck Jentzsch
2023-04-27 12:20:30 +02:00
parent 00b0f101ac
commit 1672b01e62
4 changed files with 215 additions and 12 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/iss/arch/riscv_hart_m_p.h
View File

@ -422,6 +422,15 @@ protected:
feature_config cfg;
unsigned mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
replace_mem_access(std::function<mem_read_f> rd, std::function<mem_write_f> wr){
std::pair<std::function<mem_read_f>, std::function<mem_write_f>> ret{hart_mem_rd_delegate, hart_mem_wr_delegate};
hart_mem_rd_delegate = rd;
hart_mem_wr_delegate = wr;
return ret;
}
std::function<mem_read_f> hart_mem_rd_delegate;
std::function<mem_write_f> hart_mem_wr_delegate;
};
template <typename BASE, features_e FEAT>
@ -543,6 +552,12 @@ riscv_hart_m_p<BASE, FEAT>::riscv_hart_m_p(feature_config cfg)
csr_wr_cb[dcsr] = &this_class::write_dcsr_dcsr;
csr_rd_cb[dcsr] = &this_class::read_dcsr_reg;
}
hart_mem_rd_delegate = [this](phys_addr_t a, unsigned l, uint8_t* const d) -> iss::status {
return this->read_mem(a, l, d);
};
hart_mem_wr_delegate = [this](phys_addr_t a, unsigned l, uint8_t const* const d) -> iss::status {
return this->write_mem(a, l, d);
};
}
template <typename BASE, features_e FEAT> std::pair<uint64_t, bool> riscv_hart_m_p<BASE, FEAT>::load_file(std::string name, int type) {
@ -663,9 +678,9 @@ iss::status riscv_hart_m_p<BASE, FEAT>::read(const address_type type, const acce
auto idx = std::distance(std::begin(memfn_range), it);
res = memfn_read[idx](phys_addr, length, data);
} else
res = read_mem( phys_addr, length, data);
res = hart_mem_rd_delegate( phys_addr, length, data);
} else {
res = read_mem( phys_addr, length, data);
res = hart_mem_rd_delegate( phys_addr, length, data);
}
if (unlikely(res != iss::Ok)){
this->trap_state = (1UL << 31) | (5 << 16); // issue trap 5 (load access fault