Streamline arch descriptions according to latest CoreDSL changes
This commit is contained in:
parent
65ceedd157
commit
142654b0a2
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@ -0,0 +1,34 @@
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
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<launchConfiguration type="org.eclipse.cdt.launch.applicationLaunchType">
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<booleanAttribute key="org.eclipse.cdt.dsf.gdb.AUTO_SOLIB" value="true"/>
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<listAttribute key="org.eclipse.cdt.dsf.gdb.AUTO_SOLIB_LIST"/>
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<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="gdb"/>
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<booleanAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_ON_FORK" value="false"/>
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<stringAttribute key="org.eclipse.cdt.dsf.gdb.GDB_INIT" value=".gdbinit"/>
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<booleanAttribute key="org.eclipse.cdt.dsf.gdb.NON_STOP" value="false"/>
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<booleanAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE" value="false"/>
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<stringAttribute key="org.eclipse.cdt.dsf.gdb.REVERSE_MODE" value="UseSoftTrace"/>
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<listAttribute key="org.eclipse.cdt.dsf.gdb.SOLIB_PATH"/>
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<stringAttribute key="org.eclipse.cdt.dsf.gdb.TRACEPOINT_MODE" value="TP_NORMAL_ONLY"/>
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<booleanAttribute key="org.eclipse.cdt.dsf.gdb.UPDATE_THREADLIST_ON_SUSPEND" value="false"/>
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<booleanAttribute key="org.eclipse.cdt.dsf.gdb.internal.ui.launching.LocalApplicationCDebuggerTab.DEFAULTS_SET" value="true"/>
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<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
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<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
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<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_ID" value="gdb"/>
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<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_START_MODE" value="run"/>
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<booleanAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN" value="true"/>
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<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_STOP_AT_MAIN_SYMBOL" value="main"/>
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<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_ARGUMENTS" value="-v4 ${project_loc:dhrystone}/dhrystone"/>
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<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="build/Release/riscv/bin/riscv"/>
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<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="DBT-RISE-RISCV"/>
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<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="false"/>
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<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value=""/>
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<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
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<listEntry value="/DBT-RISE-RISCV"/>
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</listAttribute>
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<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
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<listEntry value="4"/>
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</listAttribute>
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<stringAttribute key="org.eclipse.dsf.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList context="reserved-for-future-use"/> "/>
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<stringAttribute key="process_factory_id" value="org.eclipse.cdt.dsf.gdb.GdbProcessFactory"/>
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</launchConfiguration>
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@ -2,7 +2,7 @@ import "RV32IBase.core_desc"
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InsructionSet RV32D extends RV32IBase{
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InsructionSet RV32D extends RV32IBase{
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constants {
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constants {
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FLEN, FFLAG_MASK
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FLEN, FFLAG_MASK := 0x1f
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}
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}
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registers {
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registers {
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[31:0] F[FLEN], FCSR[32]
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[31:0] F[FLEN], FCSR[32]
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@ -2,7 +2,7 @@ import "RV32IBase.core_desc"
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InsructionSet RV32F extends RV32IBase{
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InsructionSet RV32F extends RV32IBase{
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constants {
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constants {
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FLEN, FFLAG_MASK
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FLEN, FFLAG_MASK := 0x1f
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}
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}
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registers {
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registers {
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[31:0] F[FLEN], FCSR[32]
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[31:0] F[FLEN], FCSR[32]
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@ -1,12 +1,12 @@
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InsructionSet RV32IBase {
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InsructionSet RV32IBase {
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constants {
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constants {
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XLEN,
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XLEN,
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XLEN_BIT_MASK,
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PCLEN,
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PCLEN,
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fence,
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XLEN_BIT_MASK:=0x1f,
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fencei,
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fence:=0,
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fencevmal,
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fencei:=1,
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fencevmau
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fencevmal:=2,
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fencevmau:=3
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}
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}
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address_spaces {
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address_spaces {
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@ -2,14 +2,14 @@ import "RV32IBase.core_desc"
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InsructionSet RV32M extends RV32IBase {
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InsructionSet RV32M extends RV32IBase {
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constants {
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constants {
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XLEN2
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MAXLEN:=128
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}
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}
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instructions{
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instructions{
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MUL{
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MUL{
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0){
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if(rd != 0){
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val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
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val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
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X[rd]<= zext(res , XLEN);
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X[rd]<= zext(res , XLEN);
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}
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}
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}
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}
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@ -17,7 +17,7 @@ InsructionSet RV32M extends RV32IBase {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0){
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if(rd != 0){
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val res[XLEN2] <= sext(X[rs1], XLEN2) * sext(X[rs2], XLEN2);
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val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN);
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X[rd]<= zext(res >> XLEN, XLEN);
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X[rd]<= zext(res >> XLEN, XLEN);
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}
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}
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}
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}
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@ -25,7 +25,7 @@ InsructionSet RV32M extends RV32IBase {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0){
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if(rd != 0){
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val res[XLEN2] <= sext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
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val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
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X[rd]<= zext(res >> XLEN, XLEN);
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X[rd]<= zext(res >> XLEN, XLEN);
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}
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}
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}
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}
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@ -33,7 +33,7 @@ InsructionSet RV32M extends RV32IBase {
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
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encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011;
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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args_disass:"x%rd$d, x%rs1$d, x%rs2$d";
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if(rd != 0){
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if(rd != 0){
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val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2);
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val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN);
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X[rd]<= zext(res >> XLEN, XLEN);
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X[rd]<= zext(res >> XLEN, XLEN);
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}
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}
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}
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}
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@ -13,15 +13,10 @@ Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
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template:"vm_riscv.in.cpp";
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template:"vm_riscv.in.cpp";
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constants {
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constants {
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XLEN:=32;
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XLEN:=32;
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XLEN2:=64;
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XLEN_BIT_MASK:=0x1f;
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PCLEN:=32;
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PCLEN:=32;
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fence:=0;
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// definitions for the architecture wrapper
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fencei:=1;
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fencevmal:=2;
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fencevmau:=3;
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100000001;
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MISA_VAL:=0b01000000000101000001000100000101;
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PGSIZE := 4096; //1 << 12;
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PGSIZE := 4096; //1 << 12;
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PGMASK := 4095; //PGSIZE-1
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PGMASK := 4095; //PGSIZE-1
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}
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}
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@ -31,18 +26,12 @@ Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32
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constants {
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constants {
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XLEN:=32;
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XLEN:=32;
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FLEN:=64;
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FLEN:=64;
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XLEN2:=64;
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XLEN_BIT_MASK:=0x1f;
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PCLEN:=32;
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PCLEN:=32;
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fence:=0;
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// definitions for the architecture wrapper
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fencei:=1;
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fencevmal:=2;
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fencevmau:=3;
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b01000000000101000001000100000001;
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MISA_VAL:=0b01000000000101000001000100101101;
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PGSIZE := 4096; //1 << 12;
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PGSIZE := 4096; //1 << 12;
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PGMASK := 4095; //PGSIZE-1
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PGMASK := 4095; //PGSIZE-1
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FFLAG_MASK:=0x1f;
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}
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}
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}
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}
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@ -51,13 +40,8 @@ Core RV64IA provides RV64IBase, RV64A, RV32A {
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template:"vm_riscv.in.cpp";
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template:"vm_riscv.in.cpp";
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constants {
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constants {
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XLEN:=64;
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XLEN:=64;
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XLEN2:=128;
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XLEN_BIT_MASK:=0x3f;
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PCLEN:=64;
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PCLEN:=64;
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fence:=0;
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// definitions for the architecture wrapper
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fencei:=1;
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fencevmal:=2;
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fencevmau:=3;
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b10000000000001000000000100000001;
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MISA_VAL:=0b10000000000001000000000100000001;
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PGSIZE := 4096; //1 << 12;
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PGSIZE := 4096; //1 << 12;
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@ -48,7 +48,7 @@ struct traits<rv32gc> {
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constexpr static char const* const core_type = "RV32GC";
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constexpr static char const* const core_type = "RV32GC";
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enum constants {XLEN=32, FLEN=64, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095, FFLAG_MASK=31};
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enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=1075056941, PGSIZE=4096, PGMASK=4095};
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constexpr static unsigned FP_REGS_SIZE = 64;
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constexpr static unsigned FP_REGS_SIZE = 64;
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@ -48,7 +48,7 @@ struct traits<rv32imac> {
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constexpr static char const* const core_type = "RV32IMAC";
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constexpr static char const* const core_type = "RV32IMAC";
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enum constants {XLEN=32, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095};
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enum constants {XLEN=32, PCLEN=32, MISA_VAL=1075056901, PGSIZE=4096, PGMASK=4095};
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constexpr static unsigned FP_REGS_SIZE = 0;
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constexpr static unsigned FP_REGS_SIZE = 0;
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@ -48,7 +48,7 @@ struct traits<rv64ia> {
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constexpr static char const* const core_type = "RV64IA";
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constexpr static char const* const core_type = "RV64IA";
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enum constants {XLEN=64, XLEN2=128, XLEN_BIT_MASK=63, PCLEN=64, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
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enum constants {XLEN=64, PCLEN=64, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095};
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constexpr static unsigned FP_REGS_SIZE = 0;
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constexpr static unsigned FP_REGS_SIZE = 0;
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@ -2578,11 +2578,11 @@ private:
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Value* res_val = this->builder.CreateMul(
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Value* res_val = this->builder.CreateMul(
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this->gen_ext(
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this->gen_ext(
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this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
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this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
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64,
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128,
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false),
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false),
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this->gen_ext(
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this->gen_ext(
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this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
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this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
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64,
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128,
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false));
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false));
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Value* X_rd_val = this->gen_ext(
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Value* X_rd_val = this->gen_ext(
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res_val,
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res_val,
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@ -2625,11 +2625,11 @@ private:
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Value* res_val = this->builder.CreateMul(
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Value* res_val = this->builder.CreateMul(
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this->gen_ext(
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this->gen_ext(
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this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
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this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
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64,
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128,
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true),
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true),
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this->gen_ext(
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this->gen_ext(
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this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
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this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
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64,
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128,
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true));
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true));
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Value* X_rd_val = this->gen_ext(
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Value* X_rd_val = this->gen_ext(
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this->builder.CreateLShr(
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this->builder.CreateLShr(
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@ -2674,11 +2674,11 @@ private:
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Value* res_val = this->builder.CreateMul(
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Value* res_val = this->builder.CreateMul(
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this->gen_ext(
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this->gen_ext(
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this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
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this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
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64,
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128,
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true),
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true),
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this->gen_ext(
|
this->gen_ext(
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this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
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64,
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128,
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false));
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false));
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Value* X_rd_val = this->gen_ext(
|
Value* X_rd_val = this->gen_ext(
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this->builder.CreateLShr(
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this->builder.CreateLShr(
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@ -2723,11 +2723,11 @@ private:
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Value* res_val = this->builder.CreateMul(
|
Value* res_val = this->builder.CreateMul(
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this->gen_ext(
|
this->gen_ext(
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this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
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this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
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64,
|
128,
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false),
|
false),
|
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this->gen_ext(
|
this->gen_ext(
|
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this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
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64,
|
128,
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false));
|
false));
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Value* X_rd_val = this->gen_ext(
|
Value* X_rd_val = this->gen_ext(
|
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this->builder.CreateLShr(
|
this->builder.CreateLShr(
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|
|
|
@ -2458,11 +2458,11 @@ private:
|
||||||
Value* res_val = this->builder.CreateMul(
|
Value* res_val = this->builder.CreateMul(
|
||||||
this->gen_ext(
|
this->gen_ext(
|
||||||
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
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64,
|
128,
|
||||||
false),
|
false),
|
||||||
this->gen_ext(
|
this->gen_ext(
|
||||||
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
||||||
64,
|
128,
|
||||||
false));
|
false));
|
||||||
Value* X_rd_val = this->gen_ext(
|
Value* X_rd_val = this->gen_ext(
|
||||||
res_val,
|
res_val,
|
||||||
|
@ -2505,11 +2505,11 @@ private:
|
||||||
Value* res_val = this->builder.CreateMul(
|
Value* res_val = this->builder.CreateMul(
|
||||||
this->gen_ext(
|
this->gen_ext(
|
||||||
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
||||||
64,
|
128,
|
||||||
true),
|
true),
|
||||||
this->gen_ext(
|
this->gen_ext(
|
||||||
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
||||||
64,
|
128,
|
||||||
true));
|
true));
|
||||||
Value* X_rd_val = this->gen_ext(
|
Value* X_rd_val = this->gen_ext(
|
||||||
this->builder.CreateLShr(
|
this->builder.CreateLShr(
|
||||||
|
@ -2554,11 +2554,11 @@ private:
|
||||||
Value* res_val = this->builder.CreateMul(
|
Value* res_val = this->builder.CreateMul(
|
||||||
this->gen_ext(
|
this->gen_ext(
|
||||||
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
||||||
64,
|
128,
|
||||||
true),
|
true),
|
||||||
this->gen_ext(
|
this->gen_ext(
|
||||||
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
||||||
64,
|
128,
|
||||||
false));
|
false));
|
||||||
Value* X_rd_val = this->gen_ext(
|
Value* X_rd_val = this->gen_ext(
|
||||||
this->builder.CreateLShr(
|
this->builder.CreateLShr(
|
||||||
|
@ -2603,11 +2603,11 @@ private:
|
||||||
Value* res_val = this->builder.CreateMul(
|
Value* res_val = this->builder.CreateMul(
|
||||||
this->gen_ext(
|
this->gen_ext(
|
||||||
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
||||||
64,
|
128,
|
||||||
false),
|
false),
|
||||||
this->gen_ext(
|
this->gen_ext(
|
||||||
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
||||||
64,
|
128,
|
||||||
false));
|
false));
|
||||||
Value* X_rd_val = this->gen_ext(
|
Value* X_rd_val = this->gen_ext(
|
||||||
this->builder.CreateLShr(
|
this->builder.CreateLShr(
|
||||||
|
|
|
@ -2128,7 +2128,7 @@ private:
|
||||||
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
||||||
this->builder.CreateAnd(
|
this->builder.CreateAnd(
|
||||||
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
||||||
this->gen_const(64U, 63)));
|
this->gen_const(64U, 31)));
|
||||||
this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
|
this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
|
||||||
}
|
}
|
||||||
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||||||
|
@ -2298,7 +2298,7 @@ private:
|
||||||
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
||||||
this->builder.CreateAnd(
|
this->builder.CreateAnd(
|
||||||
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
||||||
this->gen_const(64U, 63)));
|
this->gen_const(64U, 31)));
|
||||||
this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
|
this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
|
||||||
}
|
}
|
||||||
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||||||
|
@ -2337,7 +2337,7 @@ private:
|
||||||
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs1_val + traits<ARCH>::X0, 0),
|
||||||
this->builder.CreateAnd(
|
this->builder.CreateAnd(
|
||||||
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
this->gen_reg_load(fld_rs2_val + traits<ARCH>::X0, 0),
|
||||||
this->gen_const(64U, 63)));
|
this->gen_const(64U, 31)));
|
||||||
this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
|
this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits<ARCH>::X0), false);
|
||||||
}
|
}
|
||||||
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
this->gen_set_pc(pc, traits<ARCH>::NEXT_PC);
|
||||||
|
|
Loading…
Reference in New Issue