From 142654b0a24c630a63a799fe45b9befccc019501 Mon Sep 17 00:00:00 2001 From: Eyck Jentzsch Date: Tue, 24 Apr 2018 17:18:24 +0200 Subject: [PATCH] Streamline arch descriptions according to latest CoreDSL changes --- etc/dbt-riscv dhrystone.launch | 34 +++++++++++++++++++++++++++++ riscv/gen_input/RV32D.core_desc | 2 +- riscv/gen_input/RV32F.core_desc | 2 +- riscv/gen_input/RV32IBase.core_desc | 10 ++++----- riscv/gen_input/RV32M.core_desc | 10 ++++----- riscv/gen_input/minres_rv.core_desc | 26 +++++----------------- riscv/incl/iss/arch/rv32gc.h | 2 +- riscv/incl/iss/arch/rv32imac.h | 2 +- riscv/incl/iss/arch/rv64ia.h | 2 +- riscv/src/internal/vm_rv32gc.cpp | 16 +++++++------- riscv/src/internal/vm_rv32imac.cpp | 16 +++++++------- riscv/src/internal/vm_rv64ia.cpp | 6 ++--- 12 files changed, 73 insertions(+), 55 deletions(-) create mode 100644 etc/dbt-riscv dhrystone.launch diff --git a/etc/dbt-riscv dhrystone.launch b/etc/dbt-riscv dhrystone.launch new file mode 100644 index 0000000..a00fc10 --- /dev/null +++ b/etc/dbt-riscv dhrystone.launch @@ -0,0 +1,34 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/riscv/gen_input/RV32D.core_desc b/riscv/gen_input/RV32D.core_desc index faf2b7b..56c1262 100644 --- a/riscv/gen_input/RV32D.core_desc +++ b/riscv/gen_input/RV32D.core_desc @@ -2,7 +2,7 @@ import "RV32IBase.core_desc" InsructionSet RV32D extends RV32IBase{ constants { - FLEN, FFLAG_MASK + FLEN, FFLAG_MASK := 0x1f } registers { [31:0] F[FLEN], FCSR[32] diff --git a/riscv/gen_input/RV32F.core_desc b/riscv/gen_input/RV32F.core_desc index 3a41db7..a5324fd 100644 --- a/riscv/gen_input/RV32F.core_desc +++ b/riscv/gen_input/RV32F.core_desc @@ -2,7 +2,7 @@ import "RV32IBase.core_desc" InsructionSet RV32F extends RV32IBase{ constants { - FLEN, FFLAG_MASK + FLEN, FFLAG_MASK := 0x1f } registers { [31:0] F[FLEN], FCSR[32] diff --git a/riscv/gen_input/RV32IBase.core_desc b/riscv/gen_input/RV32IBase.core_desc index bbf4a79..22f02f7 100644 --- a/riscv/gen_input/RV32IBase.core_desc +++ b/riscv/gen_input/RV32IBase.core_desc @@ -1,12 +1,12 @@ InsructionSet RV32IBase { constants { XLEN, - XLEN_BIT_MASK, PCLEN, - fence, - fencei, - fencevmal, - fencevmau + XLEN_BIT_MASK:=0x1f, + fence:=0, + fencei:=1, + fencevmal:=2, + fencevmau:=3 } address_spaces { diff --git a/riscv/gen_input/RV32M.core_desc b/riscv/gen_input/RV32M.core_desc index b2d88fa..2296923 100644 --- a/riscv/gen_input/RV32M.core_desc +++ b/riscv/gen_input/RV32M.core_desc @@ -2,14 +2,14 @@ import "RV32IBase.core_desc" InsructionSet RV32M extends RV32IBase { constants { - XLEN2 + MAXLEN:=128 } instructions{ MUL{ encoding: b0000001 | rs2[4:0] | rs1[4:0] | b000 | rd[4:0] | b0110011; args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; if(rd != 0){ - val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2); + val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN); X[rd]<= zext(res , XLEN); } } @@ -17,7 +17,7 @@ InsructionSet RV32M extends RV32IBase { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b001 | rd[4:0] | b0110011; args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; if(rd != 0){ - val res[XLEN2] <= sext(X[rs1], XLEN2) * sext(X[rs2], XLEN2); + val res[MAXLEN] <= sext(X[rs1], MAXLEN) * sext(X[rs2], MAXLEN); X[rd]<= zext(res >> XLEN, XLEN); } } @@ -25,7 +25,7 @@ InsructionSet RV32M extends RV32IBase { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b010 | rd[4:0] | b0110011; args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; if(rd != 0){ - val res[XLEN2] <= sext(X[rs1], XLEN2) * zext(X[rs2], XLEN2); + val res[MAXLEN] <= sext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN); X[rd]<= zext(res >> XLEN, XLEN); } } @@ -33,7 +33,7 @@ InsructionSet RV32M extends RV32IBase { encoding: b0000001 | rs2[4:0] | rs1[4:0] | b011 | rd[4:0] | b0110011; args_disass:"x%rd$d, x%rs1$d, x%rs2$d"; if(rd != 0){ - val res[XLEN2] <= zext(X[rs1], XLEN2) * zext(X[rs2], XLEN2); + val res[MAXLEN] <= zext(X[rs1], MAXLEN) * zext(X[rs2], MAXLEN); X[rd]<= zext(res >> XLEN, XLEN); } } diff --git a/riscv/gen_input/minres_rv.core_desc b/riscv/gen_input/minres_rv.core_desc index a2b662b..b5d82fe 100644 --- a/riscv/gen_input/minres_rv.core_desc +++ b/riscv/gen_input/minres_rv.core_desc @@ -13,15 +13,10 @@ Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC { template:"vm_riscv.in.cpp"; constants { XLEN:=32; - XLEN2:=64; - XLEN_BIT_MASK:=0x1f; PCLEN:=32; - fence:=0; - fencei:=1; - fencevmal:=2; - fencevmau:=3; + // definitions for the architecture wrapper // XL ZYXWVUTSRQPONMLKJIHGFEDCBA - MISA_VAL:=0b01000000000101000001000100000001; + MISA_VAL:=0b01000000000101000001000100000101; PGSIZE := 4096; //1 << 12; PGMASK := 4095; //PGSIZE-1 } @@ -31,18 +26,12 @@ Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32 constants { XLEN:=32; FLEN:=64; - XLEN2:=64; - XLEN_BIT_MASK:=0x1f; PCLEN:=32; - fence:=0; - fencei:=1; - fencevmal:=2; - fencevmau:=3; + // definitions for the architecture wrapper // XL ZYXWVUTSRQPONMLKJIHGFEDCBA - MISA_VAL:=0b01000000000101000001000100000001; + MISA_VAL:=0b01000000000101000001000100101101; PGSIZE := 4096; //1 << 12; PGMASK := 4095; //PGSIZE-1 - FFLAG_MASK:=0x1f; } } @@ -51,13 +40,8 @@ Core RV64IA provides RV64IBase, RV64A, RV32A { template:"vm_riscv.in.cpp"; constants { XLEN:=64; - XLEN2:=128; - XLEN_BIT_MASK:=0x3f; PCLEN:=64; - fence:=0; - fencei:=1; - fencevmal:=2; - fencevmau:=3; + // definitions for the architecture wrapper // XL ZYXWVUTSRQPONMLKJIHGFEDCBA MISA_VAL:=0b10000000000001000000000100000001; PGSIZE := 4096; //1 << 12; diff --git a/riscv/incl/iss/arch/rv32gc.h b/riscv/incl/iss/arch/rv32gc.h index 297aaaa..0f9d93e 100644 --- a/riscv/incl/iss/arch/rv32gc.h +++ b/riscv/incl/iss/arch/rv32gc.h @@ -48,7 +48,7 @@ struct traits { constexpr static char const* const core_type = "RV32GC"; - enum constants {XLEN=32, FLEN=64, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095, FFLAG_MASK=31}; + enum constants {XLEN=32, FLEN=64, PCLEN=32, MISA_VAL=1075056941, PGSIZE=4096, PGMASK=4095}; constexpr static unsigned FP_REGS_SIZE = 64; diff --git a/riscv/incl/iss/arch/rv32imac.h b/riscv/incl/iss/arch/rv32imac.h index 5e8924b..571b758 100644 --- a/riscv/incl/iss/arch/rv32imac.h +++ b/riscv/incl/iss/arch/rv32imac.h @@ -48,7 +48,7 @@ struct traits { constexpr static char const* const core_type = "RV32IMAC"; - enum constants {XLEN=32, XLEN2=64, XLEN_BIT_MASK=31, PCLEN=32, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=1075056897, PGSIZE=4096, PGMASK=4095}; + enum constants {XLEN=32, PCLEN=32, MISA_VAL=1075056901, PGSIZE=4096, PGMASK=4095}; constexpr static unsigned FP_REGS_SIZE = 0; diff --git a/riscv/incl/iss/arch/rv64ia.h b/riscv/incl/iss/arch/rv64ia.h index 1c2b12d..10a8989 100644 --- a/riscv/incl/iss/arch/rv64ia.h +++ b/riscv/incl/iss/arch/rv64ia.h @@ -48,7 +48,7 @@ struct traits { constexpr static char const* const core_type = "RV64IA"; - enum constants {XLEN=64, XLEN2=128, XLEN_BIT_MASK=63, PCLEN=64, fence=0, fencei=1, fencevmal=2, fencevmau=3, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095}; + enum constants {XLEN=64, PCLEN=64, MISA_VAL=2147746049, PGSIZE=4096, PGMASK=4095}; constexpr static unsigned FP_REGS_SIZE = 0; diff --git a/riscv/src/internal/vm_rv32gc.cpp b/riscv/src/internal/vm_rv32gc.cpp index 854952c..5514005 100644 --- a/riscv/src/internal/vm_rv32gc.cpp +++ b/riscv/src/internal/vm_rv32gc.cpp @@ -2578,11 +2578,11 @@ private: Value* res_val = this->builder.CreateMul( this->gen_ext( this->gen_reg_load(fld_rs1_val + traits::X0, 0), - 64, + 128, false), this->gen_ext( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - 64, + 128, false)); Value* X_rd_val = this->gen_ext( res_val, @@ -2625,11 +2625,11 @@ private: Value* res_val = this->builder.CreateMul( this->gen_ext( this->gen_reg_load(fld_rs1_val + traits::X0, 0), - 64, + 128, true), this->gen_ext( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - 64, + 128, true)); Value* X_rd_val = this->gen_ext( this->builder.CreateLShr( @@ -2674,11 +2674,11 @@ private: Value* res_val = this->builder.CreateMul( this->gen_ext( this->gen_reg_load(fld_rs1_val + traits::X0, 0), - 64, + 128, true), this->gen_ext( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - 64, + 128, false)); Value* X_rd_val = this->gen_ext( this->builder.CreateLShr( @@ -2723,11 +2723,11 @@ private: Value* res_val = this->builder.CreateMul( this->gen_ext( this->gen_reg_load(fld_rs1_val + traits::X0, 0), - 64, + 128, false), this->gen_ext( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - 64, + 128, false)); Value* X_rd_val = this->gen_ext( this->builder.CreateLShr( diff --git a/riscv/src/internal/vm_rv32imac.cpp b/riscv/src/internal/vm_rv32imac.cpp index daa48da..cd0cce9 100644 --- a/riscv/src/internal/vm_rv32imac.cpp +++ b/riscv/src/internal/vm_rv32imac.cpp @@ -2458,11 +2458,11 @@ private: Value* res_val = this->builder.CreateMul( this->gen_ext( this->gen_reg_load(fld_rs1_val + traits::X0, 0), - 64, + 128, false), this->gen_ext( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - 64, + 128, false)); Value* X_rd_val = this->gen_ext( res_val, @@ -2505,11 +2505,11 @@ private: Value* res_val = this->builder.CreateMul( this->gen_ext( this->gen_reg_load(fld_rs1_val + traits::X0, 0), - 64, + 128, true), this->gen_ext( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - 64, + 128, true)); Value* X_rd_val = this->gen_ext( this->builder.CreateLShr( @@ -2554,11 +2554,11 @@ private: Value* res_val = this->builder.CreateMul( this->gen_ext( this->gen_reg_load(fld_rs1_val + traits::X0, 0), - 64, + 128, true), this->gen_ext( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - 64, + 128, false)); Value* X_rd_val = this->gen_ext( this->builder.CreateLShr( @@ -2603,11 +2603,11 @@ private: Value* res_val = this->builder.CreateMul( this->gen_ext( this->gen_reg_load(fld_rs1_val + traits::X0, 0), - 64, + 128, false), this->gen_ext( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - 64, + 128, false)); Value* X_rd_val = this->gen_ext( this->builder.CreateLShr( diff --git a/riscv/src/internal/vm_rv64ia.cpp b/riscv/src/internal/vm_rv64ia.cpp index cfdfe57..b0329a5 100644 --- a/riscv/src/internal/vm_rv64ia.cpp +++ b/riscv/src/internal/vm_rv64ia.cpp @@ -2128,7 +2128,7 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(64U, 63))); + this->gen_const(64U, 31))); this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); @@ -2298,7 +2298,7 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(64U, 63))); + this->gen_const(64U, 31))); this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC); @@ -2337,7 +2337,7 @@ private: this->gen_reg_load(fld_rs1_val + traits::X0, 0), this->builder.CreateAnd( this->gen_reg_load(fld_rs2_val + traits::X0, 0), - this->gen_const(64U, 63))); + this->gen_const(64U, 31))); this->builder.CreateStore(X_rd_val, get_reg_ptr(fld_rd_val + traits::X0), false); } this->gen_set_pc(pc, traits::NEXT_PC);