DBT-RISE/DBT-RISE-TGC
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Streamline arch descriptions according to latest CoreDSL changes

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eyck committed 2018-04-24 17:18:24 +02:00
1 parent 65ceedd157
commit 142654b0a2
12 files changed
+73 -55
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riscv/gen_input/RV32F.core_desc
+1 -1
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@@ -2,7 +2,7 @@ import "RV32IBase.core_desc"
InsructionSet RV32F extends RV32IBase{
constants {
FLEN, FFLAG_MASK
FLEN, FFLAG_MASK := 0x1f
}
registers {
[31:0] F[FLEN], FCSR[32]