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adds better tohost writing implementation, allowing the standard riscv-isa-test benchmarks to run

This commit is contained in:
Eyck-Alexander Jentzsch 2024-10-21 16:46:10 +02:00
parent ad60449073
commit 0e88664ff7
1 changed files with 73 additions and 55 deletions
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128
src/iss/arch/riscv_hart_m_p.h
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@ -354,7 +354,7 @@ protected:
using csr_page_type = typename csr_type::page_type; using csr_page_type = typename csr_type::page_type;
mem_type mem; mem_type mem;
csr_type csr; csr_type csr;
std::stringstream uart_buf; std::stringstream io_buf;
std::unordered_map<reg_t, uint64_t> ptw; std::unordered_map<reg_t, uint64_t> ptw;
std::unordered_map<uint64_t, uint8_t> atomic_reservation; std::unordered_map<uint64_t, uint8_t> atomic_reservation;
std::unordered_map<unsigned, rd_csr_f> csr_rd_cb; std::unordered_map<unsigned, rd_csr_f> csr_rd_cb;
@ -446,7 +446,7 @@ riscv_hart_m_p<BASE, FEAT, LOGCAT>::riscv_hart_m_p(feature_config cfg)
csr[marchid] = traits<BASE>::MARCHID_VAL; csr[marchid] = traits<BASE>::MARCHID_VAL;
csr[mimpid] = 1; csr[mimpid] = 1;
uart_buf.str(""); io_buf.str("");
if(traits<BASE>::FLEN > 0) { if(traits<BASE>::FLEN > 0) {
csr_rd_cb[fcsr] = &this_class::read_fcsr; csr_rd_cb[fcsr] = &this_class::read_fcsr;
csr_wr_cb[fcsr] = &this_class::write_fcsr; csr_wr_cb[fcsr] = &this_class::write_fcsr;
@ -756,10 +756,10 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write(const address_type type, c
switch(addr) { switch(addr) {
case 0x10013000: // UART0 base, TXFIFO reg case 0x10013000: // UART0 base, TXFIFO reg
case 0x10023000: // UART1 base, TXFIFO reg case 0x10023000: // UART1 base, TXFIFO reg
uart_buf << (char)data[0]; io_buf << (char)data[0];
if(((char)data[0]) == '\n' || data[0] == 0) { if(((char)data[0]) == '\n' || data[0] == 0) {
std::cout << uart_buf.str(); std::cout << io_buf.str();
uart_buf.str(""); io_buf.str("");
} }
return iss::Ok; return iss::Ok;
case 0x10008000: { // HFROSC base, hfrosccfg reg case 0x10008000: { // HFROSC base, hfrosccfg reg
@ -1094,59 +1094,77 @@ iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::read_mem(phys_addr_t paddr, unsi
template <typename BASE, features_e FEAT, typename LOGCAT> template <typename BASE, features_e FEAT, typename LOGCAT>
iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) { iss::status riscv_hart_m_p<BASE, FEAT, LOGCAT>::write_mem(phys_addr_t paddr, unsigned length, const uint8_t* const data) {
switch(paddr.val) { mem_type::page_type& p = mem(paddr.val / mem.page_size);
// TODO remove UART, Peripherals should not be part of the ISS std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask));
case 0xFFFF0000: // UART0 base, TXFIFO reg // tohost handling in case of riscv-test
if(((char)data[0]) == '\n' || data[0] == 0) { // according to https://github.com/riscv-software-src/riscv-isa-sim/issues/364#issuecomment-607657754:
CPPLOG(INFO) << "UART" << ((paddr.val >> 12) & 0x3) << " send '" << uart_buf.str() << "'"; if(paddr.access && iss::access_type::FUNC) {
uart_buf.str(""); if(paddr.val == tohost) {
} else if(((char)data[0]) != '\r') if(traits<BASE>::XLEN == 32)
uart_buf << (char)data[0]; tohost &= 0x00000000ffffffff;
break; // Extract Device (bits 63:56)
default: { uint8_t device = (tohost >> 56) & 0xFF;
mem_type::page_type& p = mem(paddr.val / mem.page_size); // Extract Command (bits 55:48)
std::copy(data, data + length, p.data() + (paddr.val & mem.page_addr_mask)); uint8_t command = (tohost >> 48) & 0xFF;
// tohost handling in case of riscv-test // Extract payload (bits 47:0)
if(paddr.access && iss::access_type::FUNC) { uint64_t payload = tohost & 0xFFFFFFFFFFFFULL;
auto tohost_upper = if(payload & 1) {
(traits<BASE>::XLEN == 32 && paddr.val == (tohost + 4)) || (traits<BASE>::XLEN == 64 && paddr.val == tohost); CPPLOG(FATAL) << "tohost value is 0x" << std::hex << payload << std::dec << " (" << payload << "), stopping simulation";
auto tohost_lower = (traits<BASE>::XLEN == 32 && paddr.val == tohost) || (traits<BASE>::XLEN == 64 && paddr.val == tohost); this->reg.trap_state = std::numeric_limits<uint32_t>::max();
if(tohost_lower || tohost_upper) { this->interrupt_sim = payload;
uint64_t hostvar = *reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)); return iss::Ok;
// in case of 32 bit system, two writes to tohost are needed, only evaluate on the second (high) write } else if(device == 0 && command == 0) {
if(tohost_upper && (tohost_lower || tohost_lower_written)) { reg_t payload_addr;
switch(hostvar >> 48) { // payload contains the addr of the struct containing information about the syscall
case 0: read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload, sizeof(reg_t),
if(hostvar != 0x1) { reinterpret_cast<uint8_t*>(&payload_addr));
CPPLOG(FATAL) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar // If the payload_addr is missaligned end simulation
<< "), stopping simulation"; if(payload_addr & 1) {
} else { CPPLOG(FATAL) << "tohost payload value is 0x" << std::hex << payload_addr << std::dec << " (" << payload_addr
CPPLOG(INFO) << "tohost value is 0x" << std::hex << hostvar << std::dec << " (" << hostvar << "), stopping simulation";
<< "), stopping simulation"; this->reg.trap_state = std::numeric_limits<uint32_t>::max();
} this->interrupt_sim = payload;
this->reg.trap_state = std::numeric_limits<uint32_t>::max(); return iss::Ok;
this->interrupt_sim = hostvar; }
break; // read the entire struct into an array
case 0x0101: { reg_t loaded_payload[8];
char c = static_cast<char>(hostvar & 0xff); read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, payload_addr, sizeof(loaded_payload),
if(c == '\n' || c == 0) { reinterpret_cast<uint8_t*>(loaded_payload));
CPPLOG(INFO) << "tohost send '" << uart_buf.str() << "'"; reg_t syscall_no = loaded_payload[0];
uart_buf.str(""); if(syscall_no == 64) { // SYS_WRITE
} else reg_t fd = loaded_payload[1];
uart_buf << c; reg_t buf_ptr = loaded_payload[2];
} break; reg_t len = loaded_payload[3];
default: std::vector<char> buf(len);
break; read(address_type::PHYSICAL, access_type::READ, traits<BASE>::MEM, buf_ptr, len,
reinterpret_cast<uint8_t*>(buf.data()));
// we disregard the fd and just log to stdout
for(size_t i = 0; i < len; i++) {
io_buf << buf[i];
} }
tohost_lower_written = false; CPPLOG(INFO) << "tohost send '" << io_buf.str() << "'";
} else if(tohost_lower) io_buf.str("");
tohost_lower_written = true; // Not sure what the correct return value should be
} else if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) { uint8_t ret_val = 1;
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask)); write(address_type::PHYSICAL, access_type::WRITE, traits<BASE>::MEM, fromhost, 1, &ret_val);
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar; } else {
CPPLOG(ERR) << "tohost syscall with number " << std::hex << syscall_no << std::dec << " (" << syscall_no
<< ") not implemented";
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload;
return iss::Ok;
}
} else {
CPPLOG(ERR) << "tohost functionality not implemented for device " << device << " and command " << command;
this->reg.trap_state = std::numeric_limits<uint32_t>::max();
this->interrupt_sim = payload;
return iss::Ok;
} }
} }
} if((traits<BASE>::XLEN == 32 && paddr.val == fromhost + 4) || (traits<BASE>::XLEN == 64 && paddr.val == fromhost)) {
uint64_t fhostvar = *reinterpret_cast<uint64_t*>(p.data() + (fromhost & mem.page_addr_mask));
*reinterpret_cast<uint64_t*>(p.data() + (tohost & mem.page_addr_mask)) = fhostvar;
}
} }
return iss::Ok; return iss::Ok;
} }