changes [m|u]cause rd/wr handling
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@ -419,7 +419,7 @@ protected:
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std::vector<std::function<mem_write_f>> memfn_write;
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void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
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feature_config cfg;
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unsigned mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
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uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
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inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
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std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
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replace_mem_access(std::function<mem_read_f> rd, std::function<mem_write_f> wr){
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@ -966,12 +966,11 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>
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val |= state.mstatus.MPIE<<27;
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val |= state.mstatus.MPP<<28;
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} else
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val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
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val = csr[addr]; // & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
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return iss::Ok;
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}
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template <typename BASE, features_e FEAT> iss::status riscv_hart_m_p<BASE, FEAT>::write_cause(unsigned addr, reg_t val) {
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csr[addr] = val & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
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if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) {
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auto mask = ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16));
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csr[addr] = (val & mask) | (csr[addr] & ~mask);
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@ -446,7 +446,7 @@ protected:
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std::vector<std::function<mem_write_f>> memfn_write;
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void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
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feature_config cfg;
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unsigned mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
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uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
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inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
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std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
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@ -1148,7 +1148,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
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break;
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}
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} else
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val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
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val = csr[addr];// & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
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return iss::Ok;
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}
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