diff --git a/src/iss/arch/riscv_hart_m_p.h b/src/iss/arch/riscv_hart_m_p.h index 1111146..beb0cc2 100644 --- a/src/iss/arch/riscv_hart_m_p.h +++ b/src/iss/arch/riscv_hart_m_p.h @@ -419,7 +419,7 @@ protected: std::vector> memfn_write; void insert_mem_range(uint64_t, uint64_t, std::function, std::function); feature_config cfg; - unsigned mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16}; + uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16}; inline bool debug_mode_active() {return this->reg.PRIV&0x4;} std::pair, std::function> replace_mem_access(std::function rd, std::function wr){ @@ -966,12 +966,11 @@ template iss::status riscv_hart_m_p val |= state.mstatus.MPIE<<27; val |= state.mstatus.MPP<<28; } else - val = csr[addr] & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); + val = csr[addr]; // & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); return iss::Ok; } template iss::status riscv_hart_m_p::write_cause(unsigned addr, reg_t val) { - csr[addr] = val & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); if((FEAT & features_e::FEAT_CLIC) && (csr[mtvec]&0x3)==3) { auto mask = ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1) | (0xfUL<<16)); csr[addr] = (val & mask) | (csr[addr] & ~mask); diff --git a/src/iss/arch/riscv_hart_mu_p.h b/src/iss/arch/riscv_hart_mu_p.h index 513ca20..0dc0de7 100644 --- a/src/iss/arch/riscv_hart_mu_p.h +++ b/src/iss/arch/riscv_hart_mu_p.h @@ -446,7 +446,7 @@ protected: std::vector> memfn_write; void insert_mem_range(uint64_t, uint64_t, std::function, std::function); feature_config cfg; - unsigned mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16}; + uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16}; inline bool debug_mode_active() {return this->reg.PRIV&0x4;} std::pair, std::function> @@ -1148,7 +1148,7 @@ template iss::status riscv_hart_mu_p::XLEN-1)) | (mcause_max_irq-1)); + val = csr[addr];// & ((1UL<<(traits::XLEN-1)) | (mcause_max_irq-1)); return iss::Ok; }