DBT-RISE/DBT-RISE-TGC
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changes [m|u]cause rd/wr handling

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Eyck Jentzsch
2023-06-11 18:29:48 +02:00
parent 60d07f2eb6
commit 0b5de90fb1
2 changed files with 4 additions and 5 deletions
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4
src/iss/arch/riscv_hart_mu_p.h
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@ -446,7 +446,7 @@ protected:
std::vector<std::function<mem_write_f>> memfn_write;
void insert_mem_range(uint64_t, uint64_t, std::function<mem_read_f>, std::function<mem_write_f>);
feature_config cfg;
unsigned mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
uint64_t mcause_max_irq{(FEAT&features_e::FEAT_CLIC)?4096:16};
inline bool debug_mode_active() {return this->reg.PRIV&0x4;}
std::pair<std::function<mem_read_f>, std::function<mem_write_f>>
@ -1148,7 +1148,7 @@ template <typename BASE, features_e FEAT> iss::status riscv_hart_mu_p<BASE, FEAT
break;
}
} else
val = csr[addr] & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
val = csr[addr];// & ((1UL<<(traits<BASE>::XLEN-1)) | (mcause_max_irq-1));
return iss::Ok;
}