Added plic functionality
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768df67646
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0a42c9d2ea
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@ -15,7 +15,7 @@ set(GIT_SUBMODULE_BRANCH_sc-components ${GIT_BRANCH})
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set(GIT_SUBMODULE_BRANCH_dbt-core ${GIT_BRANCH})
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include(GNUInstallDirs)
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include(cmake/Submodules.cmake)
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include(Submodules)
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#enable_testing()
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@ -33,7 +33,7 @@ find_package(Threads)
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find_package(Tcmalloc)
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set(PROJECT_3PARTY_DIRS external sr_report sr_signal)
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include(sc-components/cmake/clang-format.cmake)
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include(clang-format)
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add_subdirectory(external)
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add_subdirectory(dbt-core)
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@ -59,6 +59,8 @@ public:
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scc::memory<128_kB, 32> i_mem_ram;
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sc_core::sc_signal<sc_core::sc_time> s_clk;
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sc_core::sc_signal<bool> s_rst, s_mtime_int, s_msie_int;
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sc_core::sc_vector<sc_core::sc_signal<bool>> s_global_int;
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sc_core::sc_signal<bool> s_core_int;
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platform(sc_core::sc_module_name nm);
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@ -17,7 +17,8 @@
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#ifndef _PLIC_H_
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#define _PLIC_H_
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#include "scc/tlm_target.h"
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#include <scc/register.h>
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#include <scc/tlm_target.h>
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namespace sysc {
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@ -28,14 +29,27 @@ public:
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SC_HAS_PROCESS(plic);
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sc_core::sc_in<sc_core::sc_time> clk_i;
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sc_core::sc_in<bool> rst_i;
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sc_core::sc_vector<sc_core::sc_in<bool>> global_interrupts_i;
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sc_core::sc_out<bool> core_interrupt_o;
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sc_core::sc_event raise_int_ev;
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sc_core::sc_event clear_int_ev;
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plic(sc_core::sc_module_name nm);
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virtual ~plic() override;
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~plic() override;
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protected:
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void clock_cb();
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void reset_cb();
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void init_callbacks();
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void global_int_port_cb();
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void handle_pending_int();
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void reset_pending_int(uint32_t irq);
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void raise_core_interrupt();
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void clear_core_interrupt();
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sc_core::sc_time clk;
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std::unique_ptr<plic_regs> regs;
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std::function<bool(scc::sc_register<uint32_t>, uint32_t)> m_claim_complete_write_cb;
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};
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} /* namespace sysc */
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@ -39,7 +39,9 @@ platform::platform(sc_core::sc_module_name nm)
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, NAMED(i_mem_qspi)
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, NAMED(i_mem_ram)
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, NAMED(s_clk)
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, NAMED(s_rst) {
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, NAMED(s_rst)
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, NAMED(s_global_int, 256)
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, NAMED(s_core_int) {
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i_core_complex.initiator(i_router.target[0]);
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size_t i = 0;
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for (const auto &e : e300_plat_map) {
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@ -75,6 +77,8 @@ platform::platform(sc_core::sc_module_name nm)
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i_clint.mtime_int_o(s_mtime_int);
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i_clint.msip_int_o(s_msie_int);
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i_plic.global_interrupts_i(s_global_int);
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i_plic.core_interrupt_o(s_core_int);
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SC_THREAD(gen_reset);
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}
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@ -14,10 +14,11 @@
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// the License.
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////////////////////////////////////////////////////////////////////////////////
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#include "sysc/SiFive/plic.h"
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#include <sysc/SiFive/plic.h>
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#include "scc/utilities.h"
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#include "sysc/SiFive/gen/plic_regs.h"
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#include <scc/utilities.h>
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#include <scc/report.h>
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#include <sysc/SiFive/gen/plic_regs.h>
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namespace sysc {
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@ -26,8 +27,24 @@ plic::plic(sc_core::sc_module_name nm)
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, tlm_target<>(clk)
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, NAMED(clk_i)
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, NAMED(rst_i)
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, NAMEDD(plic_regs, regs) {
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, NAMED(global_interrupts_i, 256)
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, NAMED(core_interrupt_o)
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, NAMEDD(plic_regs, regs)
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{
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regs->registerResources(*this);
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// register callbacks
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init_callbacks();
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regs->claim_complete.set_write_cb(m_claim_complete_write_cb);
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// port callbacks
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SC_METHOD(global_int_port_cb);
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for (uint8_t i = 0; i < 255; i++) {
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sensitive << global_interrupts_i[i].pos();
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}
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dont_initialize();
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// register event callbacks
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SC_METHOD(clock_cb);
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sensitive << clk_i;
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SC_METHOD(reset_cb);
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@ -37,6 +54,16 @@ plic::plic(sc_core::sc_module_name nm)
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plic::~plic() {}
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void plic::init_callbacks() {
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m_claim_complete_write_cb = [=](scc::sc_register<uint32_t> reg, uint32_t v) -> bool {
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reg.put(v);
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reset_pending_int(v);
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// std::cout << "Value of register: 0x" << std::hex << reg << std::endl;
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// todo: reset related interrupt and find next high-prio interrupt
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return true;
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};
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}
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void plic::clock_cb() { this->clk = clk_i.read(); }
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void plic::reset_cb() {
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@ -46,4 +73,86 @@ void plic::reset_cb() {
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regs->reset_stop();
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}
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// Functional handling of interrupts:
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// - global_int_port_cb()
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// - set pending register bits
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// - called by: incoming global_int
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// - handle_pending_int()
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// - update claim register content
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// - generate core-interrupt pulse
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// - called by:
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// - incoming global_int
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// - complete-register write access
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// - reset_pending_int(int-id)
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// - reset pending bit
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// - call next handle_pending_int()
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// - called by:
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// - complete-reg write register content
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void plic::global_int_port_cb() {
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// set related pending bit if enable is set for incoming global_interrupt
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// todo: extend up to 255 bits (limited to 32 right now)
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for (uint32_t i = 1; i < 32; i++) {
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uint32_t enable_bits = regs->r_enabled;
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bool enable = enable_bits & (0x1 << i); // read enable bit
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if (enable && global_interrupts_i[i].read() == 1) {
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regs->r_pending = regs->r_pending | (0x1 << i);
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LOG(DEBUG) << "pending interrupt identified: " << i;
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}
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}
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handle_pending_int();
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}
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void plic::handle_pending_int() {
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// identify high-prio pending interrupt and raise a core-interrupt
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uint32_t claim_int = 0; // claim interrupt
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uint32_t claim_prio = 0; // related priority (highest prio interrupt wins the race)
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bool raise_int = 0;
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uint32_t thold = regs->r_threshold.threshold; // threshold value
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// todo: extend up to 255 bits (limited to 32 right now)
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for (uint32_t i = 1; i < 32; i++) {
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uint32_t pending_bits = regs->r_pending;
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bool pending = (pending_bits & (0x1 << i)) ? true : false;
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uint32_t prio = regs->r_priority[i - 1].priority; // read priority value
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if (pending && thold < prio) {
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regs->r_pending = regs->r_pending | (0x1 << i);
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// below condition ensures implicitly that lowest id is selected in case of multiple identical
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// priority-interrupts
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if (prio > claim_prio) {
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claim_prio = prio;
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claim_int = i;
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raise_int = 1;
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LOG(DEBUG) << "pending interrupt activated: " << i;
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}
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}
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}
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if (raise_int) {
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regs->r_claim_complete = claim_int;
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core_interrupt_o.write(1);
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// todo: evluate clock period
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} else {
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regs->r_claim_complete = 0;
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LOG(DEBUG) << "no further pending interrupt.";
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}
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}
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void plic::reset_pending_int(uint32_t irq) {
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// todo: evaluate enable register (see spec)
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// todo: make sure that pending is set, otherwise don't reset irq ... read spec.
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LOG(INFO) << "reset pending interrupt: " << irq;
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// reset related pending bit
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regs->r_pending &= ~(0x1 << irq);
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core_interrupt_o.write(0);
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// evaluate next pending interrupt
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handle_pending_int();
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}
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} /* namespace sysc */
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