Added custom rcmd to use with gdb 'monitor' command. Currently
implemented are 2 commands: monitor sysc print_time monitor sysc break 1 us
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8c32247aa3
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@ -50,6 +50,9 @@ class vm_if;
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namespace arch {
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template <typename BASE> struct riscv_hart_msu_vp;
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}
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namespace debugger {
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struct target_adapter_if;
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}
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}
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namespace sysc {
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@ -120,6 +123,7 @@ protected:
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std::unique_ptr<core_wrapper> cpu;
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std::unique_ptr<iss::vm_if> vm;
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sc_core::sc_time curr_clk;
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iss::debugger::target_adapter_if* tgt_adapter;
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};
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} /* namespace SiFive */
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@ -34,17 +34,24 @@
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//
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////////////////////////////////////////////////////////////////////////////////
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#include <iss/arch/riscv_hart_msu_vp.h>
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#include <iss/arch/rv32imac.h>
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#include <iss/iss.h>
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#include <iss/vm_types.h>
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#include <sysc/SiFive/core_complex.h>
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#include "scc/report.h"
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#include "iss/arch/riscv_hart_msu_vp.h"
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#include "iss/arch/rv32imac.h"
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#include "iss/iss.h"
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#include "iss/vm_types.h"
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#include "iss/debugger/server.h"
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#include "iss/debugger/gdb_session.h"
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#include "iss/debugger/target_adapter_if.h"
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#include "iss/debugger/encoderdecoder.h"
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#include "sysc/SiFive/core_complex.h"
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namespace sysc {
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namespace SiFive {
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namespace {
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iss::debugger::encoder_decoder encdec;
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}
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class core_wrapper : public iss::arch::riscv_hart_msu_vp<iss::arch::rv32imac> {
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public:
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using core_type = iss::arch::rv32imac;
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@ -73,6 +80,36 @@ private:
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core_complex *const owner;
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};
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int cmd_sysc(int argc, char* argv[], iss::debugger::out_func of, iss::debugger::data_func df, iss::debugger::target_adapter_if* tgt_adapter){
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if(argc>1) {
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if(strcasecmp(argv[1], "print_time")==0){
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std::string t = sc_core::sc_time_stamp().to_string();
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of(t.c_str());
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char buf[64];
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encdec.enc_string(t.c_str(), buf, 63);
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df(buf);
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return iss::Ok;
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} else if(strcasecmp(argv[1], "break")==0){
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sc_core::sc_time t;
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if(argc==4){
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t= scc::parse_from_string(argv[2], argv[3]);
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} else if(argc==3){
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t= scc::parse_from_string(argv[2]);
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} else
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return iss::Err;
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// no check needed as it is only called if debug server is active
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tgt_adapter->add_break_condition([t]()->unsigned{
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LOG(TRACE)<<"Checking condition at "<<sc_core::sc_time_stamp();
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return sc_core::sc_time_stamp()>=t?std::numeric_limits<unsigned>::max():0;
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});
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return iss::Ok;
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}
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return iss::Err;
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}
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return iss::Err;
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}
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void core_wrapper::notify_phase(exec_phase phase) {
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core_type::notify_phase(phase);
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if (phase == ISTART) owner->sync();
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@ -89,7 +126,8 @@ core_complex::core_complex(sc_core::sc_module_name name)
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, NAMED(gdb_server_port, 0, this)
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, NAMED(dump_ir, false, this)
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, read_lut(tlm_dmi_ext())
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, write_lut(tlm_dmi_ext()) {
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, write_lut(tlm_dmi_ext())
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, tgt_adapter(nullptr){
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initiator.register_invalidate_direct_mem_ptr([=](uint64_t start, uint64_t end) -> void {
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auto lut_entry = read_lut.getEntry(start);
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@ -115,6 +153,15 @@ void core_complex::before_end_of_elaboration() {
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cpu = std::make_unique<core_wrapper>(this);
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vm = iss::create<iss::arch::rv32imac>(cpu.get(), gdb_server_port.value, dump_ir.value);
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vm->setDisassEnabled(enable_disass.value);
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auto* srv = iss::debugger::server<iss::debugger::gdb_session>::get();
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if(srv) tgt_adapter = srv->get_target();
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if(tgt_adapter)
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tgt_adapter->add_custom_command({
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"sysc",
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[this](int argc, char* argv[], iss::debugger::out_func of, iss::debugger::data_func df)-> int {
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return cmd_sysc(argc, argv, of, df, tgt_adapter);
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},
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"SystemC sub-commands: break <time>, print_time"});
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}
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void core_complex::start_of_simulation() {
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