2017-08-27 12:10:38 +02:00
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import "RV32IBase.core_desc"
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import "RV32M.core_desc"
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import "RV32A.core_desc"
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import "RV32C.core_desc"
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2018-04-24 11:05:11 +02:00
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import "RV32F.core_desc"
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2018-04-24 15:33:21 +02:00
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import "RV32D.core_desc"
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2017-09-21 13:13:01 +02:00
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import "RV64IBase.core_desc"
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2019-01-10 11:35:20 +01:00
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import "RV64M.core_desc"
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2017-09-21 13:13:01 +02:00
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import "RV64A.core_desc"
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2017-08-27 12:10:38 +02:00
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2018-04-24 11:05:11 +02:00
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Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32IC {
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2017-08-27 12:10:38 +02:00
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constants {
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XLEN:=32;
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PCLEN:=32;
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2018-04-24 17:18:24 +02:00
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// definitions for the architecture wrapper
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2017-08-27 12:10:38 +02:00
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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2018-04-24 17:18:24 +02:00
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MISA_VAL:=0b01000000000101000001000100000101;
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2018-04-30 19:22:00 +02:00
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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2017-08-27 12:10:38 +02:00
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}
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}
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2018-04-24 15:48:42 +02:00
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Core RV32GC provides RV32IBase, RV32M, RV32A, RV32IC, RV32F, RV32FC, RV32D, RV32DC {
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2018-04-24 11:05:11 +02:00
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constants {
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XLEN:=32;
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2018-04-24 15:33:21 +02:00
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FLEN:=64;
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2018-04-24 11:05:11 +02:00
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PCLEN:=32;
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2018-04-24 17:18:24 +02:00
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// definitions for the architecture wrapper
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2018-04-24 11:05:11 +02:00
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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2018-04-24 17:18:24 +02:00
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MISA_VAL:=0b01000000000101000001000100101101;
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2018-04-30 19:22:00 +02:00
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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2018-04-24 11:05:11 +02:00
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}
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}
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2019-01-10 11:35:20 +01:00
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Core RV64I provides RV64IBase {
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constants {
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XLEN:=64;
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PCLEN:=64;
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b10000000000001000000000100000000;
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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}
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}
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2017-09-21 13:13:01 +02:00
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2019-01-10 11:35:20 +01:00
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Core RV64GC provides RV64IC, RV64A, RV64M, RV32A, RV32M, RV64F, RV64D, RV32FC, RV32DC {
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2017-08-27 12:10:38 +02:00
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constants {
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XLEN:=64;
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2019-01-10 11:35:20 +01:00
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FLEN:=64;
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2017-08-27 12:10:38 +02:00
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PCLEN:=64;
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2018-04-24 17:18:24 +02:00
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// definitions for the architecture wrapper
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2017-09-21 13:13:01 +02:00
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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2019-01-10 11:35:20 +01:00
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MISA_VAL:=0b01000000000101000001000100101101;
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2018-04-30 19:22:00 +02:00
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PGSIZE := 0x1000; //1 << 12;
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PGMASK := 0xfff; //PGSIZE-1
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2017-08-27 12:10:38 +02:00
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}
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}
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2019-01-10 11:35:20 +01:00
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