DBT-RISE-TGC/riscv/gen_input/minres_rv.core_desc

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import "RV32IBase.core_desc"
import "RV32M.core_desc"
import "RV32A.core_desc"
import "RV32C.core_desc"
import "RV64IBase.core_desc"
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//import "RV64M.core_desc"
import "RV64A.core_desc"
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Core RV32IMAC provides RV32IBase, RV32M, RV32A, RV32CI {
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template:"vm_riscv.in.cpp";
constants {
XLEN:=32;
XLEN2:=64;
XLEN_BIT_MASK:=0x1f;
PCLEN:=32;
fence:=0;
fencei:=1;
fencevmal:=2;
fencevmau:=3;
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
MISA_VAL:=0b01000000000101000001000100000001;
PGSIZE := 4096; //1 << 12;
PGMASK := 4095; //PGSIZE-1
}
}
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Core RV64IA provides RV64IBase, RV64A, RV32A {
template:"vm_riscv.in.cpp";
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constants {
XLEN:=64;
XLEN2:=128;
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XLEN_BIT_MASK:=0x3f;
PCLEN:=64;
fence:=0;
fencei:=1;
fencevmal:=2;
fencevmau:=3;
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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MISA_VAL:=0b10000000000001000000000100000001;
PGSIZE := 4096; //1 << 12;
PGMASK := 4095; //PGSIZE-1
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}
}