DBT-RISE-TGC/platform/gen_input/uart.rdl

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regfile uart_regs {
reg {
name="txdata";
desc="Transmit data register";
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field {} data[7:0];
field {} full[31:31];
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} txdata @0x00;
reg {
name="rxdata";
desc="Receive data register";
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field {} data[7:0];
field {} empty[31:31];
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}rxdata @0x04;
reg {
name="txctrl";
desc="Transmit control register";
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field {} txen[1];
field {} nstop[1];
field {} txcnt[18:16];
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}txctrl @0x08;
reg {
name="rxctrl";
desc="Receive control register";
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field {} rxen[1];
field {} rxcnt[18:16];
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}rxctrl @0x0C;
reg {
name="ie";
desc="UART interrupt enable";
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field{} txwm[1];
field{} rxwm[1];
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}ie @0x10;
reg {
name="ip";
desc="UART Interrupt pending";
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field{} txwm[1];
field{} rxwm[1];
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} ip @0x14;
reg {
name="div";
desc="Baud rate divisor";
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field{} div[16];
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} div @0x18;
};