DBT-RISE-TGC/platform/gen_input/spi.rdl

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2017-09-21 20:29:23 +02:00
regfile spi_regs {
reg {
name="sckdiv";
desc="Serial clock divisor";
field {
name ="div";
} div[12];
} sckdiv @0x000;
reg {
name="sckmode";
desc="Serial clock mode";
field {
name="pha";
} pha[1];
field {
name="pol";
} pol[1];
} sckmode @0x004;
reg {
name="csid";
desc="Chip select ID";
field {
name="csid";
} csid[32];
} csid @0x010;
reg {
name="csdef";
desc="Chip select default";
field {
name="csdef";
} csdef[32];
} csdef @0x014;
reg {
name="csmode";
desc="Chip select mode";
field {
name="mode";
} mode[2];
} csmode @0x018;
reg {
name="delay0";
desc="Delay control 0";
field {
name="cssck";
} cssck[7:0];
field {
name ="sckcs";
} sckcs[23:16];
} delay0 @0x028;
reg {
name="delay1";
desc="Delay control 1";
field {
name="intercs";
}intercs[15:0];
field {
name="interxfr";
} interxfr[23:16];
} delay1 @0x02C;
reg {
name="fmt";
desc="Frame format";
field{
name ="proto";
}proto[2];
field {
name="endian";
} endian[1];
field {
name="dir";
} dir[1];
field {
name="len";
} len[19:16];
} fmt @0x040;
reg {
name="txdata";
desc="Tx FIFO data";
field {
name="data";
} data[8];
field {
name="full";
} full[31:31];
} txdata @0x048;
reg {
name="rxdata";
desc="Rx FIFO data";
field{
name="data";
} data[8];
field{
name="empty";
} empty[31:31];
} rxdata @0x04C;
reg {
name="txmark";
desc="Tx FIFO watermark";
field {
name="txmark";
} txmark[3];
} txmark @0x050;
reg {
name="rxmark";
desc="Rx FIFO watermark";
field {
name="rxmark";
} rxmark[3];
} rxmark @0x054;
reg {
name="fctrl";
desc="SPI flash interface control";
field {
name="en";
} en[1];
} fctrl @0x060;
reg {
name="ffmt";
desc="SPI flash instruction format";
field {
name="cmd_en";
reset=0x1;
} cmd_en[1];
field {
name="addr_len";
reset=0x3;
} addr_len[2];
field {
name="pad_cnt";
reset=0x0;
} pad_cnt[4];
field {
name="cmd_proto";
reset=0x0;
} cmd_proto[2];
field {
name="addr_proto";
reset=0x0;
} addr_proto[2];
field {
name="data_proto";
reset=0x0;
} data_proto[2];
field {
name="cmd_code";
reset=0x3;
} cmd_code[23:16];
field {
name="pad_code";
reset=0x0;
} pad_code[8];
} ffmt @0x064;
reg {
name="ie";
desc="SPI interrupt enable";
field{
name="txwm";
} txwm[1];
field{
name="rxwm";
} rxwm[1];
} ie @0x070;
reg {
name="ip";
desc="SPI interrupt pending";
field{
name="txwm";
} txwm[1];
field{
name="rxwm";
} rxwm[1];
} ip @0x074;
};