2023-08-27 15:17:12 +02:00
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import "ISA/RVI.core_desc"
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2023-05-27 10:20:49 +02:00
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import "ISA/RVM.core_desc"
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import "ISA/RVC.core_desc"
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2021-09-04 12:46:56 +02:00
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2023-08-27 15:17:12 +02:00
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Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
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2021-09-04 12:46:56 +02:00
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architectural_state {
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2021-09-29 00:03:11 +02:00
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XLEN=32;
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2021-09-04 12:46:56 +02:00
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// definitions for the architecture wrapper
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// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
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2023-05-27 10:20:49 +02:00
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unsigned int MISA_VAL = 0b01000000000000000001000100000100;
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unsigned int MARCHID_VAL = 0x80000003;
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2021-09-04 12:46:56 +02:00
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}
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}
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