DBT-RISE-TGC/gen_input/TGC5C.core_desc

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import "ISA/RVI.core_desc"
import "ISA/RVM.core_desc"
import "ISA/RVC.core_desc"
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Core TGC5C provides RV32I, Zicsr, Zifencei, RV32M, RV32IC {
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architectural_state {
XLEN=32;
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// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned int MISA_VAL = 0b01000000000000000001000100000100;
unsigned int MARCHID_VAL = 0x80000003;
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}
}