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DBT-RISE-TGC/src/vm/interp/vm_tgf_c.cpp

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Initial setup
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/*******************************************************************************
* Copyright (C) 2020 MINRES Technologies GmbH
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. Neither the name of the copyright holder nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
*******************************************************************************/
get all compile clean
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#include "../fp_functions.h"
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#include <iss/arch/tgf_c.h>
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#include <iss/arch/riscv_hart_m_p.h>
Initial setup
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#include <iss/debugger/gdb_session.h>
#include <iss/debugger/server.h>
#include <iss/iss.h>
#include <iss/interp/vm_base.h>
#include <util/logging.h>
#include <sstream>
#ifndef FMT_HEADER_ONLY
#define FMT_HEADER_ONLY
#endif
#include <fmt/format.h>
#include <array>
#include <iss/debugger/riscv_target_adapter.h>
namespace iss {
namespace interp {
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namespace tgf_c {
Initial setup
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using namespace iss::arch;
using namespace iss::debugger;
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template <typename ARCH> class vm_impl : public iss::interp::vm_base<ARCH> {
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public:
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using traits = arch::traits<ARCH>;
using super = typename iss::interp::vm_base<ARCH>;
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using virt_addr_t = typename super::virt_addr_t;
using phys_addr_t = typename super::phys_addr_t;
using code_word_t = typename super::code_word_t;
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using addr_t = typename super::addr_t;
using reg_t = typename traits::reg_t;
using mem_type_e = typename traits::mem_type_e;
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vm_impl();
vm_impl(ARCH &core, unsigned core_id = 0, unsigned cluster_id = 0);
void enableDebug(bool enable) { super::sync_exec = super::ALL_SYNC; }
target_adapter_if *accquire_target_adapter(server_if *srv) override {
debugger_if::dbg_enabled = true;
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if (super::tgt_adapter == nullptr)
super::tgt_adapter = new riscv_target_adapter<ARCH>(srv, this->get_arch());
return super::tgt_adapter;
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}
protected:
using this_class = vm_impl<ARCH>;
using compile_ret_t = virt_addr_t;
using compile_func = compile_ret_t (this_class::*)(virt_addr_t &pc, code_word_t instr);
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inline const char *name(size_t index){return traits::reg_aliases.at(index);}
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virt_addr_t execute_inst(virt_addr_t start, std::function<bool(void)> pred) override;
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// some compile time constants
// enum { MASK16 = 0b1111110001100011, MASK32 = 0b11111111111100000111000001111111 };
enum { MASK16 = 0b1111111111111111, MASK32 = 0b11111111111100000111000001111111 };
enum { EXTR_MASK16 = MASK16 >> 2, EXTR_MASK32 = MASK32 >> 2 };
enum { LUT_SIZE = 1 << util::bit_count(EXTR_MASK32), LUT_SIZE_C = 1 << util::bit_count(EXTR_MASK16) };
std::array<compile_func, LUT_SIZE> lut;
std::array<compile_func, LUT_SIZE_C> lut_00, lut_01, lut_10;
std::array<compile_func, LUT_SIZE> lut_11;
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std::array<compile_func *, 4> qlut;
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std::array<const uint32_t, 4> lutmasks = {{EXTR_MASK16, EXTR_MASK16, EXTR_MASK16, EXTR_MASK32}};
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void expand_bit_mask(int pos, uint32_t mask, uint32_t value, uint32_t valid, uint32_t idx, compile_func lut[],
compile_func f) {
if (pos < 0) {
lut[idx] = f;
} else {
auto bitmask = 1UL << pos;
if ((mask & bitmask) == 0) {
expand_bit_mask(pos - 1, mask, value, valid, idx, lut, f);
} else {
if ((valid & bitmask) == 0) {
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1), lut, f);
expand_bit_mask(pos - 1, mask, value, valid, (idx << 1) + 1, lut, f);
} else {
auto new_val = idx << 1;
if ((value & bitmask) != 0) new_val++;
expand_bit_mask(pos - 1, mask, value, valid, new_val, lut, f);
}
}
}
}
inline uint32_t extract_fields(uint32_t val) { return extract_fields(29, val >> 2, lutmasks[val & 0x3], 0); }
uint32_t extract_fields(int pos, uint32_t val, uint32_t mask, uint32_t lut_val) {
if (pos >= 0) {
auto bitmask = 1UL << pos;
if ((mask & bitmask) == 0) {
lut_val = extract_fields(pos - 1, val, mask, lut_val);
} else {
auto new_val = lut_val << 1;
if ((val & bitmask) != 0) new_val++;
lut_val = extract_fields(pos - 1, val, mask, new_val);
}
}
return lut_val;
}
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void raise(uint16_t trap_id, uint16_t cause){
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auto trap_val = 0x80ULL << 24 | (cause << 16) | trap_id;
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this->template get_reg<uint32_t>(traits::TRAP_STATE) = trap_val;
this->template get_reg<uint32_t>(traits::NEXT_PC) = std::numeric_limits<uint32_t>::max();
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}
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void leave(unsigned lvl){
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this->core.leave_trap(lvl);
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auto pc_val = super::template read_mem<reg_t>(traits::CSR, (lvl << 8) + 0x41);
this->template get_reg<reg_t>(traits::NEXT_PC) = pc_val;
this->template get_reg<uint32_t>(traits::LAST_BRANCH) = std::numeric_limits<uint32_t>::max();
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}
void wait(unsigned type){
this->core.wait_until(type);
}
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inline uint8_t readSpace1(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint8_t>(space, addr);}
inline uint16_t readSpace2(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint16_t>(space, addr);}
inline uint32_t readSpace4(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint32_t>(space, addr);}
inline uint64_t readSpace8(typename super::mem_type_e space, uint64_t addr){return super::template read_mem<uint64_t>(space, addr);}
inline void writeSpace1(typename super::mem_type_e space, uint64_t addr, uint8_t data){super::write_mem(space, addr, data);}
inline void writeSpace2(typename super::mem_type_e space, uint64_t addr, uint16_t data){super::write_mem(space, addr, data);}
inline void writeSpace4(typename super::mem_type_e space, uint64_t addr, uint32_t data){super::write_mem(space, addr, data);}
inline void writeSpace8(typename super::mem_type_e space, uint64_t addr, uint64_t data){super::write_mem(space, addr, data);}
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Initial setup
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private:
/****************************************************************************
* start opcode definitions
****************************************************************************/
struct InstructionDesriptor {
size_t length;
uint32_t value;
uint32_t mask;
compile_func op;
};
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const std::array<InstructionDesriptor, 88> instr_descr = {{
Initial setup
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/* entries are: size, valid value, valid mask, function ptr */
/* instruction LUI */
{32, 0b00000000000000000000000000110111, 0b00000000000000000000000001111111, &this_class::__lui},
/* instruction AUIPC */
{32, 0b00000000000000000000000000010111, 0b00000000000000000000000001111111, &this_class::__auipc},
/* instruction JAL */
{32, 0b00000000000000000000000001101111, 0b00000000000000000000000001111111, &this_class::__jal},
/* instruction JALR */
{32, 0b00000000000000000000000001100111, 0b00000000000000000111000001111111, &this_class::__jalr},
/* instruction BEQ */
{32, 0b00000000000000000000000001100011, 0b00000000000000000111000001111111, &this_class::__beq},
/* instruction BNE */
{32, 0b00000000000000000001000001100011, 0b00000000000000000111000001111111, &this_class::__bne},
/* instruction BLT */
{32, 0b00000000000000000100000001100011, 0b00000000000000000111000001111111, &this_class::__blt},
/* instruction BGE */
{32, 0b00000000000000000101000001100011, 0b00000000000000000111000001111111, &this_class::__bge},
/* instruction BLTU */
{32, 0b00000000000000000110000001100011, 0b00000000000000000111000001111111, &this_class::__bltu},
/* instruction BGEU */
{32, 0b00000000000000000111000001100011, 0b00000000000000000111000001111111, &this_class::__bgeu},
/* instruction LB */
{32, 0b00000000000000000000000000000011, 0b00000000000000000111000001111111, &this_class::__lb},
/* instruction LH */
{32, 0b00000000000000000001000000000011, 0b00000000000000000111000001111111, &this_class::__lh},
/* instruction LW */
{32, 0b00000000000000000010000000000011, 0b00000000000000000111000001111111, &this_class::__lw},
/* instruction LBU */
{32, 0b00000000000000000100000000000011, 0b00000000000000000111000001111111, &this_class::__lbu},
/* instruction LHU */
{32, 0b00000000000000000101000000000011, 0b00000000000000000111000001111111, &this_class::__lhu},
/* instruction SB */
{32, 0b00000000000000000000000000100011, 0b00000000000000000111000001111111, &this_class::__sb},
/* instruction SH */
{32, 0b00000000000000000001000000100011, 0b00000000000000000111000001111111, &this_class::__sh},
/* instruction SW */
{32, 0b00000000000000000010000000100011, 0b00000000000000000111000001111111, &this_class::__sw},
/* instruction ADDI */
{32, 0b00000000000000000000000000010011, 0b00000000000000000111000001111111, &this_class::__addi},
/* instruction SLTI */
{32, 0b00000000000000000010000000010011, 0b00000000000000000111000001111111, &this_class::__slti},
/* instruction SLTIU */
{32, 0b00000000000000000011000000010011, 0b00000000000000000111000001111111, &this_class::__sltiu},
/* instruction XORI */
{32, 0b00000000000000000100000000010011, 0b00000000000000000111000001111111, &this_class::__xori},
/* instruction ORI */
{32, 0b00000000000000000110000000010011, 0b00000000000000000111000001111111, &this_class::__ori},
/* instruction ANDI */
{32, 0b00000000000000000111000000010011, 0b00000000000000000111000001111111, &this_class::__andi},
/* instruction SLLI */
{32, 0b00000000000000000001000000010011, 0b11111110000000000111000001111111, &this_class::__slli},
/* instruction SRLI */
{32, 0b00000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srli},
/* instruction SRAI */
{32, 0b01000000000000000101000000010011, 0b11111110000000000111000001111111, &this_class::__srai},
/* instruction ADD */
{32, 0b00000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__add},
/* instruction SUB */
{32, 0b01000000000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__sub},
/* instruction SLL */
{32, 0b00000000000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__sll},
/* instruction SLT */
{32, 0b00000000000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__slt},
/* instruction SLTU */
{32, 0b00000000000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__sltu},
/* instruction XOR */
{32, 0b00000000000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__xor},
/* instruction SRL */
{32, 0b00000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__srl},
/* instruction SRA */
{32, 0b01000000000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__sra},
/* instruction OR */
{32, 0b00000000000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__or},
/* instruction AND */
{32, 0b00000000000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__and},
/* instruction FENCE */
{32, 0b00000000000000000000000000001111, 0b11110000000000000111000001111111, &this_class::__fence},
/* instruction FENCE_I */
{32, 0b00000000000000000001000000001111, 0b00000000000000000111000001111111, &this_class::__fence_i},
/* instruction ECALL */
{32, 0b00000000000000000000000001110011, 0b11111111111111111111111111111111, &this_class::__ecall},
/* instruction EBREAK */
{32, 0b00000000000100000000000001110011, 0b11111111111111111111111111111111, &this_class::__ebreak},
/* instruction URET */
{32, 0b00000000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__uret},
/* instruction SRET */
{32, 0b00010000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__sret},
/* instruction MRET */
{32, 0b00110000001000000000000001110011, 0b11111111111111111111111111111111, &this_class::__mret},
/* instruction WFI */
{32, 0b00010000010100000000000001110011, 0b11111111111111111111111111111111, &this_class::__wfi},
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/* instruction SFENCE_VMA */
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{32, 0b00010010000000000000000001110011, 0b11111110000000000111111111111111, &this_class::__sfence_vma},
/* instruction CSRRW */
{32, 0b00000000000000000001000001110011, 0b00000000000000000111000001111111, &this_class::__csrrw},
/* instruction CSRRS */
{32, 0b00000000000000000010000001110011, 0b00000000000000000111000001111111, &this_class::__csrrs},
/* instruction CSRRC */
{32, 0b00000000000000000011000001110011, 0b00000000000000000111000001111111, &this_class::__csrrc},
/* instruction CSRRWI */
{32, 0b00000000000000000101000001110011, 0b00000000000000000111000001111111, &this_class::__csrrwi},
/* instruction CSRRSI */
{32, 0b00000000000000000110000001110011, 0b00000000000000000111000001111111, &this_class::__csrrsi},
/* instruction CSRRCI */
{32, 0b00000000000000000111000001110011, 0b00000000000000000111000001111111, &this_class::__csrrci},
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/* instruction MUL */
{32, 0b00000010000000000000000000110011, 0b11111110000000000111000001111111, &this_class::__mul},
/* instruction MULH */
{32, 0b00000010000000000001000000110011, 0b11111110000000000111000001111111, &this_class::__mulh},
/* instruction MULHSU */
{32, 0b00000010000000000010000000110011, 0b11111110000000000111000001111111, &this_class::__mulhsu},
/* instruction MULHU */
{32, 0b00000010000000000011000000110011, 0b11111110000000000111000001111111, &this_class::__mulhu},
/* instruction DIV */
{32, 0b00000010000000000100000000110011, 0b11111110000000000111000001111111, &this_class::__div},
/* instruction DIVU */
{32, 0b00000010000000000101000000110011, 0b11111110000000000111000001111111, &this_class::__divu},
/* instruction REM */
{32, 0b00000010000000000110000000110011, 0b11111110000000000111000001111111, &this_class::__rem},
/* instruction REMU */
{32, 0b00000010000000000111000000110011, 0b11111110000000000111000001111111, &this_class::__remu},
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/* instruction CADDI4SPN */
{16, 0b0000000000000000, 0b1110000000000011, &this_class::__caddi4spn},
/* instruction CLW */
{16, 0b0100000000000000, 0b1110000000000011, &this_class::__clw},
/* instruction CSW */
{16, 0b1100000000000000, 0b1110000000000011, &this_class::__csw},
/* instruction CADDI */
{16, 0b0000000000000001, 0b1110000000000011, &this_class::__caddi},
/* instruction CNOP */
{16, 0b0000000000000001, 0b1111111111111111, &this_class::__cnop},
/* instruction CJAL */
{16, 0b0010000000000001, 0b1110000000000011, &this_class::__cjal},
/* instruction CLI */
{16, 0b0100000000000001, 0b1110000000000011, &this_class::__cli},
/* instruction CLUI */
{16, 0b0110000000000001, 0b1110000000000011, &this_class::__clui},
/* instruction CADDI16SP */
{16, 0b0110000100000001, 0b1110111110000011, &this_class::__caddi16sp},
/* instruction CSRLI */
{16, 0b1000000000000001, 0b1111110000000011, &this_class::__csrli},
/* instruction CSRAI */
{16, 0b1000010000000001, 0b1111110000000011, &this_class::__csrai},
/* instruction CANDI */
{16, 0b1000100000000001, 0b1110110000000011, &this_class::__candi},
/* instruction CSUB */
{16, 0b1000110000000001, 0b1111110001100011, &this_class::__csub},
/* instruction CXOR */
{16, 0b1000110000100001, 0b1111110001100011, &this_class::__cxor},
/* instruction COR */
{16, 0b1000110001000001, 0b1111110001100011, &this_class::__cor},
/* instruction CAND */
{16, 0b1000110001100001, 0b1111110001100011, &this_class::__cand},
/* instruction CJ */
{16, 0b1010000000000001, 0b1110000000000011, &this_class::__cj},
/* instruction CBEQZ */
{16, 0b1100000000000001, 0b1110000000000011, &this_class::__cbeqz},
/* instruction CBNEZ */
{16, 0b1110000000000001, 0b1110000000000011, &this_class::__cbnez},
/* instruction CSLLI */
{16, 0b0000000000000010, 0b1111000000000011, &this_class::__cslli},
/* instruction CLWSP */
{16, 0b0100000000000010, 0b1110000000000011, &this_class::__clwsp},
/* instruction CMV */
{16, 0b1000000000000010, 0b1111000000000011, &this_class::__cmv},
/* instruction CJR */
{16, 0b1000000000000010, 0b1111000001111111, &this_class::__cjr},
/* instruction CADD */
{16, 0b1001000000000010, 0b1111000000000011, &this_class::__cadd},
/* instruction CJALR */
{16, 0b1001000000000010, 0b1111000001111111, &this_class::__cjalr},
/* instruction CEBREAK */
{16, 0b1001000000000010, 0b1111111111111111, &this_class::__cebreak},
/* instruction CSWSP */
{16, 0b1100000000000010, 0b1110000000000011, &this_class::__cswsp},
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/* instruction DII */
{16, 0b0000000000000000, 0b1111111111111111, &this_class::__dii},
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}};
/* instruction definitions */
/* instruction 0: LUI */
compile_ret_t __lui(virt_addr_t& pc, code_word_t instr){
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// pre execution stuff
this->do_sync(PRE_SYNC, 0);
uint8_t rd = ((bit_sub<7,5>(instr)));
int32_t imm = signextend<int32_t,32>((bit_sub<12,20>(instr) << 12));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "lui"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 0);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
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}
/* instruction 1: AUIPC */
compile_ret_t __auipc(virt_addr_t& pc, code_word_t instr){
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// pre execution stuff
this->do_sync(PRE_SYNC, 1);
uint8_t rd = ((bit_sub<7,5>(instr)));
int32_t imm = signextend<int32_t,32>((bit_sub<12,20>(instr) << 12));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#08x}", fmt::arg("mnemonic", "auipc"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *PC + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 1);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 2: JAL */
compile_ret_t __jal(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 2);
uint8_t rd = ((bit_sub<7,5>(instr)));
int32_t imm = signextend<int32_t,21>((bit_sub<12,8>(instr) << 12) | (bit_sub<20,1>(instr) << 11) | (bit_sub<21,10>(instr) << 1) | (bit_sub<31,1>(instr) << 20));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#0x}", fmt::arg("mnemonic", "jal"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd != 0) *(X+rd) = *PC + 4;
*PC = *PC + imm;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 2);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 3: JALR */
compile_ret_t __jalr(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 3);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {imm:#0x}", fmt::arg("mnemonic", "jalr"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
int32_t new_pc = *(X+rs1) + imm;
if(rd != 0) *(X+rd) = *PC + 4;
*PC = new_pc & ~ 0x1;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 3);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 4: BEQ */
compile_ret_t __beq(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 4);
int16_t imm = signextend<int16_t,13>((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "beq"),
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) == *(X+rs2)? *PC + imm : *PC + 4;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 4);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 5: BNE */
compile_ret_t __bne(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 5);
int16_t imm = signextend<int16_t,13>((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bne"),
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) != *(X+rs2)? *PC + imm : *PC + 4;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 5);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 6: BLT */
compile_ret_t __blt(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 6);
int16_t imm = signextend<int16_t,13>((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "blt"),
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) < *(X+rs2)? *PC + imm : *PC + 4;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 6);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 7: BGE */
compile_ret_t __bge(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 7);
int16_t imm = signextend<int16_t,13>((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bge"),
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) >= *(X+rs2)? *PC + imm : *PC + 4;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 7);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 8: BLTU */
compile_ret_t __bltu(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 8);
int16_t imm = signextend<int16_t,13>((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bltu"),
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) < *(X+rs2)? *PC + imm : *PC + 4;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 8);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 9: BGEU */
compile_ret_t __bgeu(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 9);
int16_t imm = signextend<int16_t,13>((bit_sub<7,1>(instr) << 11) | (bit_sub<8,4>(instr) << 1) | (bit_sub<25,6>(instr) << 5) | (bit_sub<31,1>(instr) << 12));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rs2}, {imm:#0x}", fmt::arg("mnemonic", "bgeu"),
fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1) >= *(X+rs2)? *PC + imm : *PC + 4;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 9);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 10: LB */
compile_ret_t __lb(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 10);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lb"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = readSpace1(traits::MEM, *(X+rs1) + imm);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 10);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 11: LH */
compile_ret_t __lh(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 11);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lh"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = (int16_t)readSpace2(traits::MEM, *(X+rs1) + imm);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 11);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 12: LW */
compile_ret_t __lw(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 12);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lw"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = (int32_t)readSpace4(traits::MEM, *(X+rs1) + imm);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 12);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 13: LBU */
compile_ret_t __lbu(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 13);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lbu"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = (uint8_t)readSpace1(traits::MEM, *(X+rs1) + imm);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 13);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 14: LHU */
compile_ret_t __lhu(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 14);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm}({rs1})", fmt::arg("mnemonic", "lhu"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = (uint16_t)readSpace2(traits::MEM, *(X+rs1) + imm);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 14);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 15: SB */
compile_ret_t __sb(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 15);
int16_t imm = signextend<int16_t,12>((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sb"),
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
writeSpace1(traits::MEM, *(X+rs1) + imm, (int8_t)*(X+rs2));
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 15);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 16: SH */
compile_ret_t __sh(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 16);
int16_t imm = signextend<int16_t,12>((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sh"),
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
writeSpace2(traits::MEM, *(X+rs1) + imm, (int16_t)*(X+rs2));
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 16);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 17: SW */
compile_ret_t __sw(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 17);
int16_t imm = signextend<int16_t,12>((bit_sub<7,5>(instr)) | (bit_sub<25,7>(instr) << 5));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {imm}({rs1})", fmt::arg("mnemonic", "sw"),
fmt::arg("rs2", name(rs2)), fmt::arg("imm", imm), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
writeSpace4(traits::MEM, *(X+rs1) + imm, *(X+rs2));
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 17);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 18: ADDI */
compile_ret_t __addi(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 18);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "addi"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 18);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 19: SLTI */
compile_ret_t __slti(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 19);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "slti"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) < imm? 1 : 0;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 19);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 20: SLTIU */
compile_ret_t __sltiu(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 20);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "sltiu"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = (uint8_t)*(X+rs1) < (uint8_t)(int32_t)imm? 1 : 0;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 20);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 21: XORI */
compile_ret_t __xori(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 21);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "xori"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) ^ imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 21);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 22: ORI */
compile_ret_t __ori(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 22);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "ori"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) | imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 22);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 23: ANDI */
compile_ret_t __andi(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 23);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
int16_t imm = signextend<int16_t,12>((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {imm}", fmt::arg("mnemonic", "andi"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) & imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 23);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
[WIP] first working version
2020-01-12 18:19:48 +01:00
}
/* instruction 24: SLLI */
compile_ret_t __slli(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 24);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t shamt = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "slli"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(shamt > 31) {
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = *(X+rs1) << shamt;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 24);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
[WIP] first working version
2020-01-12 18:19:48 +01:00
}
/* instruction 25: SRLI */
compile_ret_t __srli(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 25);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t shamt = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srli"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(shamt > 31) {
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = ((uint8_t)*(X+rs1)) >> shamt;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 25);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
[WIP] first working version
2020-01-12 18:19:48 +01:00
}
/* instruction 26: SRAI */
Initial setup
2020-01-10 07:24:00 +01:00
compile_ret_t __srai(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 26);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t shamt = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {shamt}", fmt::arg("mnemonic", "srai"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(shamt > 31) {
raise(0, 0);
}
else {
if(rd != 0) *(X+rd) = *(X+rs1) >> shamt;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 26);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 27: ADD */
compile_ret_t __add(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 27);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "add"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) + *(X+rs2);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 27);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 28: SUB */
compile_ret_t __sub(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 28);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sub"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) - *(X+rs2);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 28);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 29: SLL */
compile_ret_t __sll(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 29);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sll"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1));
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 29);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 30: SLT */
compile_ret_t __slt(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 30);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "slt"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) < *(X+rs2)? 1 : 0;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 30);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 31: SLTU */
compile_ret_t __sltu(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 31);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sltu"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = (uint32_t)*(X+rs1) < (uint32_t)*(X+rs2)? 1 : 0;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 31);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 32: XOR */
compile_ret_t __xor(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 32);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "xor"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) ^ *(X+rs2);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 32);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 33: SRL */
compile_ret_t __srl(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 33);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "srl"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) << (*(X+rs2) & (traits::XLEN - 1));
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 33);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 34: SRA */
compile_ret_t __sra(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 34);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "sra"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) >> (*(X+rs2) & (traits::XLEN - 1));
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 34);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 35: OR */
compile_ret_t __or(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 35);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "or"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) | *(X+rs2);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 35);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 36: AND */
compile_ret_t __and(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 36);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "and"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
if(rd != 0) *(X+rd) = *(X+rs1) & *(X+rs2);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 36);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 37: FENCE */
compile_ret_t __fence(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 37);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t succ = ((bit_sub<20,4>(instr)));
uint8_t pred = ((bit_sub<24,4>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
update RISC-V descriptions
2021-02-15 19:01:33 +01:00
auto mnemonic = fmt::format(
"{mnemonic:10} {pred}, {succ}, {rs1}, {rd}", fmt::arg("mnemonic", "fence"),
fmt::arg("pred", name(pred)), fmt::arg("succ", name(succ)), fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)));
this->core.disass_output(pc.val, mnemonic);
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
writeSpace1(traits::FENCE, traits::fence, pred << 4 | succ);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 37);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 38: FENCE_I */
compile_ret_t __fence_i(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 38);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint16_t imm = ((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
update RISC-V descriptions
2021-02-15 19:01:33 +01:00
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {rd}, {imm}", fmt::arg("mnemonic", "fence_i"),
fmt::arg("rs1", name(rs1)), fmt::arg("rd", name(rd)), fmt::arg("imm", name(imm)));
this->core.disass_output(pc.val, mnemonic);
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
writeSpace2(traits::FENCE, traits::fencei, imm);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 38);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 39: ECALL */
compile_ret_t __ecall(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 39);
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "ecall");
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
raise(0, 11);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 39);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 40: EBREAK */
compile_ret_t __ebreak(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 40);
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "ebreak");
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
raise(0, 3);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 40);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 41: URET */
compile_ret_t __uret(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 41);
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "uret");
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
leave(0);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 41);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 42: SRET */
compile_ret_t __sret(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 42);
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "sret");
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
leave(1);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 42);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 43: MRET */
compile_ret_t __mret(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 43);
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "mret");
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
leave(3);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 43);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 44: WFI */
compile_ret_t __wfi(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 44);
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "wfi");
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
wait(1);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 44);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 45: SFENCE_VMA */
Initial setup
2020-01-10 07:24:00 +01:00
compile_ret_t __sfence_vma(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 45);
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
update RISC-V descriptions
2021-02-15 19:01:33 +01:00
auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {rs1}", fmt::arg("mnemonic", "sfence_vma"),
fmt::arg("rs2", name(rs2)), fmt::arg("rs1", rs1));
this->core.disass_output(pc.val, mnemonic);
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
writeSpace1(traits::FENCE, traits::fencevmal, (uint8_t)rs1);
writeSpace1(traits::FENCE, traits::fencevmau, (uint8_t)rs2);
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 45);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 46: CSRRW */
compile_ret_t __csrrw(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 46);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint16_t csr = ((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrw"),
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint32_t rs_val = *(X+rs1);
if(rd != 0) {
uint32_t csr_val = readSpace4(traits::CSR, csr);
writeSpace4(traits::CSR, csr, rs_val);
*(X+rd) = csr_val;
}
else {
writeSpace4(traits::CSR, csr, rs_val);
}
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 46);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
[WIP] first working version
2020-01-12 18:19:48 +01:00
}
/* instruction 47: CSRRS */
compile_ret_t __csrrs(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 47);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint16_t csr = ((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrs"),
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint32_t xrd = readSpace4(traits::CSR, csr);
uint32_t xrs1 = *(X+rs1);
if(rd != 0) *(X+rd) = xrd;
if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd | xrs1);
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 47);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
[WIP] first working version
2020-01-12 18:19:48 +01:00
}
/* instruction 48: CSRRC */
compile_ret_t __csrrc(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 48);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint16_t csr = ((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {csr}, {rs1}", fmt::arg("mnemonic", "csrrc"),
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint32_t xrd = readSpace4(traits::CSR, csr);
uint32_t xrs1 = *(X+rs1);
if(rd != 0) *(X+rd) = xrd;
if(rs1 != 0) writeSpace4(traits::CSR, csr, xrd & ~ xrs1);
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 48);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
[WIP] first working version
2020-01-12 18:19:48 +01:00
}
Initial setup
2020-01-10 07:24:00 +01:00
/* instruction 49: CSRRWI */
compile_ret_t __csrrwi(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 49);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t zimm = ((bit_sub<15,5>(instr)));
uint16_t csr = ((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrwi"),
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd != 0) *(X+rd) = readSpace4(traits::CSR, csr);
writeSpace4(traits::CSR, csr, (uint32_t)zimm);
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 49);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 50: CSRRSI */
compile_ret_t __csrrsi(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 50);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t zimm = ((bit_sub<15,5>(instr)));
uint16_t csr = ((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrsi"),
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint32_t res = readSpace4(traits::CSR, csr);
if(zimm != 0) writeSpace4(traits::CSR, csr, res | (uint32_t)zimm);
if(rd != 0) *(X+rd) = res;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 50);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/* instruction 51: CSRRCI */
compile_ret_t __csrrci(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 51);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t zimm = ((bit_sub<15,5>(instr)));
uint16_t csr = ((bit_sub<20,12>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {csr}, {zimm:#0x}", fmt::arg("mnemonic", "csrrci"),
fmt::arg("rd", name(rd)), fmt::arg("csr", csr), fmt::arg("zimm", zimm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint32_t res = readSpace4(traits::CSR, csr);
if(rd != 0) *(X+rd) = res;
if(zimm != 0) writeSpace4(traits::CSR, csr, res & ~ ((uint32_t)zimm));
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 51);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
[WIP] first working version
2020-01-12 18:19:48 +01:00
}
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
2020-08-24 15:01:54 +02:00
/* instruction 52: MUL */
compile_ret_t __mul(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 52);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mul"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd != 0) {
int64_t res = (int64_t)*(X+rs1) * (int64_t)*(X+rs2);
*(X+rd) = (uint32_t)res;
}
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 52);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
2020-08-24 15:01:54 +02:00
}
/* instruction 53: MULH */
compile_ret_t __mulh(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 53);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulh"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd != 0) {
int64_t res = (int64_t)*(X+rs1) * (int64_t)*(X+rs2);
*(X+rd) = (uint32_t)(res >> traits::XLEN);
}
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 53);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
2020-08-24 15:01:54 +02:00
}
/* instruction 54: MULHSU */
compile_ret_t __mulhsu(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 54);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhsu"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd != 0) {
int64_t res = (int64_t)*(X+rs1) * (uint64_t)*(X+rs2);
*(X+rd) = (uint32_t)res;
}
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 54);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
2020-08-24 15:01:54 +02:00
}
/* instruction 55: MULHU */
compile_ret_t __mulhu(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 55);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "mulhu"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd != 0) {
uint64_t res = (uint64_t)*(X+rs1) * (uint64_t)*(X+rs2);
*(X+rd) = (uint32_t)res;
}
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 55);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
2020-08-24 15:01:54 +02:00
}
/* instruction 56: DIV */
compile_ret_t __div(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 56);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "div"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd != 0) {
if(*(X+rs2) != 0) {
uint32_t MMIN = 1 << (traits::XLEN - 1);
if(*(X+rs1) == MMIN && (int8_t)*(X+rs2) == - 1) *(X+rd) = MMIN;
else *(X+rd) = (int8_t)*(X+rs1) / (int8_t)*(X+rs2);
}
else *(X+rd) = - 1;
}
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 56);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
2020-08-24 15:01:54 +02:00
}
/* instruction 57: DIVU */
compile_ret_t __divu(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 57);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "divu"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd != 0) {
if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) / *(X+rs2);
else *(X+rd) = - 1;
}
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 57);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
2020-08-24 15:01:54 +02:00
}
/* instruction 58: REM */
compile_ret_t __rem(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 58);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "rem"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd != 0) {
if(*(X+rs2) != 0) {
uint32_t MMIN = 1 << (traits::XLEN - 1);
if(*(X+rs1) == MMIN && *(X+rs2) == - 1) *(X+rd) = 0;
else *(X+rd) = (int8_t)*(X+rs1) % (int8_t)*(X+rs2);
}
else *(X+rd) = *(X+rs1);
}
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 58);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
2020-08-24 15:01:54 +02:00
}
/* instruction 59: REMU */
compile_ret_t __remu(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 59);
uint8_t rd = ((bit_sub<7,5>(instr)));
uint8_t rs1 = ((bit_sub<15,5>(instr)));
uint8_t rs2 = ((bit_sub<20,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs1}, {rs2}", fmt::arg("mnemonic", "remu"),
fmt::arg("rd", name(rd)), fmt::arg("rs1", name(rs1)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd != 0) {
if(*(X+rs2) != 0) *(X+rd) = *(X+rs1) % *(X+rs2);
else *(X+rd) = *(X+rs1);
}
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 4;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 59);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 60: CADDI4SPN */
compile_ret_t __caddi4spn(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 60);
uint8_t rd = ((bit_sub<2,3>(instr)));
uint16_t imm = ((bit_sub<5,1>(instr) << 3) | (bit_sub<6,1>(instr) << 2) | (bit_sub<7,4>(instr) << 6) | (bit_sub<11,2>(instr) << 4));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "caddi4spn"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(imm == 0) raise(0, 2);
*(X+(rd + 8)) = *(X+2) + imm;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 60);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 61: CLW */
compile_ret_t __clw(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 61);
uint8_t rd = ((bit_sub<2,3>(instr)));
uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "clw"),
fmt::arg("rd", name(8+rd)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint32_t offs = *(X+(rs1 + 8)) + uimm;
*(X+(rd + 8)) = (int32_t)readSpace4(traits::MEM, offs);
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 61);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 62: CSW */
compile_ret_t __csw(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 62);
uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t uimm = ((bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 2) | (bit_sub<10,3>(instr) << 3));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {uimm:#05x}({rs1})", fmt::arg("mnemonic", "csw"),
fmt::arg("rs2", name(8+rs2)), fmt::arg("uimm", uimm), fmt::arg("rs1", name(8+rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint8_t offs = *(X+(rs1 + 8)) + uimm;
writeSpace4(traits::MEM, offs, *(X+(rs2 + 8)));
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 62);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 63: CADDI */
compile_ret_t __caddi(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 63);
int8_t imm = signextend<int8_t,6>((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
uint8_t rs1 = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "caddi"),
fmt::arg("rs1", name(rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*(X+rs1) = (int8_t)*(X+rs1) + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 63);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 64: CNOP */
compile_ret_t __cnop(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 64);
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "cnop");
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 64);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 65: CJAL */
compile_ret_t __cjal(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 65);
int16_t imm = signextend<int16_t,12>((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cjal"),
fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
*(X+1) = *PC + 2;
*PC = (int8_t)*PC + imm;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 65);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 66: CLI */
compile_ret_t __cli(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 66);
int8_t imm = signextend<int8_t,6>((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "cli"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd == 0) raise(0, 2);
*(X+rd) = imm;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 66);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 67: CLUI */
compile_ret_t __clui(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 67);
int32_t imm = signextend<int32_t,18>((bit_sub<2,5>(instr) << 12) | (bit_sub<12,1>(instr) << 17));
uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {imm:#05x}", fmt::arg("mnemonic", "clui"),
fmt::arg("rd", name(rd)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rd == 0) raise(0, 2);
if(imm == 0) raise(0, 2);
*(X+rd) = imm;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 67);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 68: CADDI16SP */
compile_ret_t __caddi16sp(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 68);
int16_t imm = signextend<int16_t,10>((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 7) | (bit_sub<5,1>(instr) << 6) | (bit_sub<6,1>(instr) << 4) | (bit_sub<12,1>(instr) << 9));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "caddi16sp"),
fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*(X+2) = (int8_t)*(X+2) + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 68);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 69: CSRLI */
compile_ret_t __csrli(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 69);
uint8_t shamt = ((bit_sub<2,5>(instr)));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrli"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint8_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = *(X+rs1_idx) << shamt;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 69);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 70: CSRAI */
compile_ret_t __csrai(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 70);
uint8_t shamt = ((bit_sub<2,5>(instr)));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "csrai"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint8_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = ((int8_t)*(X+rs1_idx)) >> shamt;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 70);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 71: CANDI */
compile_ret_t __candi(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 71);
int8_t imm = signextend<int8_t,6>((bit_sub<2,5>(instr)) | (bit_sub<12,1>(instr) << 5));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "candi"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint8_t rs1_idx = rs1 + 8;
*(X+rs1_idx) = *(X+rs1_idx) & imm;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 71);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 72: CSUB */
compile_ret_t __csub(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 72);
uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "csub"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint8_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) - *(X+(rs2 + 8));
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 72);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 73: CXOR */
compile_ret_t __cxor(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 73);
uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cxor"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint8_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) ^ *(X+(rs2 + 8));
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 73);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 74: COR */
compile_ret_t __cor(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 74);
uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cor"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint8_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) | *(X+(rs2 + 8));
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 74);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 75: CAND */
compile_ret_t __cand(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 75);
uint8_t rs2 = ((bit_sub<2,3>(instr)));
uint8_t rd = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cand"),
fmt::arg("rd", name(8+rd)), fmt::arg("rs2", name(8+rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint8_t rd_idx = rd + 8;
*(X+rd_idx) = *(X+rd_idx) & *(X+(rs2 + 8));
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 75);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 76: CJ */
compile_ret_t __cj(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 76);
int16_t imm = signextend<int16_t,12>((bit_sub<2,1>(instr) << 5) | (bit_sub<3,3>(instr) << 1) | (bit_sub<6,1>(instr) << 7) | (bit_sub<7,1>(instr) << 6) | (bit_sub<8,1>(instr) << 10) | (bit_sub<9,2>(instr) << 8) | (bit_sub<11,1>(instr) << 4) | (bit_sub<12,1>(instr) << 11));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {imm:#05x}", fmt::arg("mnemonic", "cj"),
fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = (int8_t)*PC + imm;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 76);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 77: CBEQZ */
compile_ret_t __cbeqz(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 77);
int16_t imm = signextend<int16_t,9>((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbeqz"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+(rs1 + 8)) == 0? (int8_t)*PC + imm : *PC + 2;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 77);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 78: CBNEZ */
compile_ret_t __cbnez(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 78);
int16_t imm = signextend<int16_t,9>((bit_sub<2,1>(instr) << 5) | (bit_sub<3,2>(instr) << 1) | (bit_sub<5,2>(instr) << 6) | (bit_sub<10,2>(instr) << 3) | (bit_sub<12,1>(instr) << 8));
uint8_t rs1 = ((bit_sub<7,3>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {imm:#05x}", fmt::arg("mnemonic", "cbnez"),
fmt::arg("rs1", name(8+rs1)), fmt::arg("imm", imm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+(rs1 + 8)) != 0? (int8_t)*PC + imm : *PC + 2;
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 78);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 79: CSLLI */
compile_ret_t __cslli(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 79);
uint8_t shamt = ((bit_sub<2,5>(instr)));
uint8_t rs1 = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}, {shamt}", fmt::arg("mnemonic", "cslli"),
fmt::arg("rs1", name(rs1)), fmt::arg("shamt", shamt));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
if(rs1 == 0) raise(0, 2);
*(X+rs1) = *(X+rs1) << shamt;
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 79);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 80: CLWSP */
compile_ret_t __clwsp(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 80);
uint8_t uimm = ((bit_sub<2,2>(instr) << 6) | (bit_sub<4,3>(instr) << 2) | (bit_sub<12,1>(instr) << 5));
uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, sp, {uimm:#05x}", fmt::arg("mnemonic", "clwsp"),
fmt::arg("rd", name(rd)), fmt::arg("uimm", uimm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint8_t offs = *(X+2) + uimm;
*(X+rd) = (int32_t)readSpace4(traits::MEM, offs);
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 80);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 81: CMV */
compile_ret_t __cmv(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 81);
uint8_t rs2 = ((bit_sub<2,5>(instr)));
uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cmv"),
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*(X+rd) = *(X+rs2);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 81);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 82: CJR */
compile_ret_t __cjr(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 82);
uint8_t rs1 = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjr"),
fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*PC = *(X+rs1);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 82);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 83: CADD */
compile_ret_t __cadd(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 83);
uint8_t rs2 = ((bit_sub<2,5>(instr)));
uint8_t rd = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rd}, {rs2}", fmt::arg("mnemonic", "cadd"),
fmt::arg("rd", name(rd)), fmt::arg("rs2", name(rs2)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
*(X+rd) = *(X+rd) + *(X+rs2);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 83);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 84: CJALR */
compile_ret_t __cjalr(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 84);
uint8_t rs1 = ((bit_sub<7,5>(instr)));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs1}", fmt::arg("mnemonic", "cjalr"),
fmt::arg("rs1", name(rs1)));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
*(X+1) = *PC + 2;
*PC = *(X+rs1);
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = super::template get_reg<reg_t>(arch::traits<ARCH>::PC);
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 84);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 85: CEBREAK */
compile_ret_t __cebreak(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 85);
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "cebreak");
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
raise(0, 3);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 85);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
}
/* instruction 86: CSWSP */
compile_ret_t __cswsp(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 86);
uint8_t rs2 = ((bit_sub<2,5>(instr)));
uint8_t uimm = ((bit_sub<7,2>(instr) << 6) | (bit_sub<9,4>(instr) << 2));
if(this->disass_enabled){
/* generate console output when executing the command */
auto mnemonic = fmt::format(
"{mnemonic:10} {rs2}, {uimm:#05x}(sp)", fmt::arg("mnemonic", "cswsp"),
fmt::arg("rs2", name(rs2)), fmt::arg("uimm", uimm));
this->core.disass_output(pc.val, mnemonic);
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
{
uint8_t offs = *(X+2) + uimm;
writeSpace4(traits::MEM, offs, (uint32_t)*(X+rs2));
}
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 86);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
[WIP] first working version
2020-01-12 18:19:48 +01:00
}
Generate and integrate TGF cores in Ecosystem-VP. Remove obsolete cores
2020-08-24 15:01:54 +02:00
/* instruction 87: DII */
[WIP] first working version
2020-01-12 18:19:48 +01:00
compile_ret_t __dii(virt_addr_t& pc, code_word_t instr){
generate working ISS from CoreDSL 2.0
2021-02-06 15:47:06 +01:00
// pre execution stuff
this->do_sync(PRE_SYNC, 87);
if(this->disass_enabled){
/* generate console output when executing the command */
this->core.disass_output(pc.val, "dii");
}
// prepare execution
uint32_t* X = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::X0]);
uint32_t* PC = reinterpret_cast<uint32_t*>(this->regs_base_ptr+arch::traits<ARCH>::reg_byte_offsets[arch::traits<ARCH>::PC]);
// execute instruction
raise(0, 2);
// post execution stuff
super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC) = pc.val + 2;
if(this->sync_exec && POST_SYNC) this->do_sync(POST_SYNC, 87);
auto& trap_state = super::template get_reg<uint32_t>(arch::traits<ARCH>::TRAP_STATE);
// trap check
if(trap_state!=0){
auto& last_br = super::template get_reg<uint32_t>(arch::traits<ARCH>::LAST_BRANCH);
last_br = std::numeric_limits<uint32_t>::max();
super::core.enter_trap(trap_state, pc.val);
}
pc.val=super::template get_reg<reg_t>(arch::traits<ARCH>::NEXT_PC);
return pc;
Initial setup
2020-01-10 07:24:00 +01:00
}
/****************************************************************************
* end opcode definitions
****************************************************************************/
compile_ret_t illegal_intruction(virt_addr_t &pc, code_word_t instr) {
pc = pc + ((instr & 3) == 3 ? 4 : 2);
return pc;
}
};
template <typename CODE_WORD> void debug_fn(CODE_WORD insn) {
volatile CODE_WORD x = insn;
insn = 2 * x;
}
template <typename ARCH> vm_impl<ARCH>::vm_impl() { this(new ARCH()); }
template <typename ARCH>
vm_impl<ARCH>::vm_impl(ARCH &core, unsigned core_id, unsigned cluster_id)
[WIP] Cleanup of namespaces etc to get compile clean
2020-01-10 09:37:48 +01:00
: vm_base<ARCH>(core, core_id, cluster_id) {
Initial setup
2020-01-10 07:24:00 +01:00
qlut[0] = lut_00.data();
qlut[1] = lut_01.data();
qlut[2] = lut_10.data();
qlut[3] = lut_11.data();
for (auto instr : instr_descr) {
auto quantrant = instr.value & 0x3;
expand_bit_mask(29, lutmasks[quantrant], instr.value >> 2, instr.mask >> 2, 0, qlut[quantrant], instr.op);
}
}
template <typename ARCH>
[WIP] first working version
2020-01-12 18:19:48 +01:00
typename vm_base<ARCH>::virt_addr_t vm_impl<ARCH>::execute_inst(virt_addr_t start, std::function<bool(void)> pred) {
Initial setup
2020-01-10 07:24:00 +01:00
// we fetch at max 4 byte, alignment is 2
enum {TRAP_ID=1<<16};
first version of tgf_c based on CoreDSL 2.0
2020-12-29 09:48:22 +01:00
const typename traits::addr_t upper_bits = ~traits::PGMASK;
[WIP] first working version
2020-01-12 18:19:48 +01:00
code_word_t insn = 0;
Initial setup
2020-01-10 07:24:00 +01:00
auto *const data = (uint8_t *)&insn;
[WIP] first working version
2020-01-12 18:19:48 +01:00
auto pc=start;
while(pred){
auto paddr = this->core.v2p(pc);
if ((pc.val & upper_bits) != ((pc.val + 2) & upper_bits)) { // we may cross a page boundary
if (this->core.read(paddr, 2, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
if ((insn & 0x3) == 0x3) // this is a 32bit instruction
if (this->core.read(this->core.v2p(pc + 2), 2, data + 2) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
} else {
if (this->core.read(paddr, 4, data) != iss::Ok) throw trap_access(TRAP_ID, pc.val);
}
if (insn == 0x0000006f || (insn&0xffff)==0xa001) throw simulation_stopped(0); // 'J 0' or 'C.J 0'
auto lut_val = extract_fields(insn);
auto f = qlut[insn & 0x3][lut_val];
if (!f)
f = &this_class::illegal_intruction;
pc = (this->*f)(pc, insn);
}
return pc;
Initial setup
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}
} // namespace mnrv32
template <>
Update TGF naming convention
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std::unique_ptr<vm_if> create<arch::tgf_c>(arch::tgf_c *core, unsigned short port, bool dump) {
auto ret = new tgf_c::vm_impl<arch::tgf_c>(*core, dump);
Initial setup
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if (port != 0) debugger::server<debugger::gdb_session>::run_server(ret, port);
return std::unique_ptr<vm_if>(ret);
}
[WIP] Cleanup of namespaces etc to get compile clean
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} // namespace interp
Initial setup
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} // namespace iss