DBT-RISE-TGC/gen_input/TGC_D.core_desc

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import "CoreDSL-Instruction-Set-Description/RV32I.core_desc"
import "CoreDSL-Instruction-Set-Description/RVM.core_desc"
import "CoreDSL-Instruction-Set-Description/RVC.core_desc"
Core TGC_D provides RV32I, RV32M, RV32IC {
architectural_state {
XLEN=32;
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// definitions for the architecture wrapper
// XL ZYXWVUTSRQPONMLKJIHGFEDCBA
unsigned MISA_VAL = 0b01000000000000000001000100000100;
unsigned MARCHID_VAL = 0x80000004;
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}
}