DBT-RISE-TGC/riscv/src/iss/rv64ia.cpp

////////////////////////////////////////////////////////////////////////////////
// Copyright (C) 2017, MINRES Technologies GmbH
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// 2. Redistributions in binary form must reproduce the above copyright notice,
//    this list of conditions and the following disclaimer in the documentation
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// Created on: Tue Sep 05 18:57:24 CEST 2017
//             *      rv64ia.cpp Author: <CoreDSL Generator>
//
////////////////////////////////////////////////////////////////////////////////

#include "util/ities.h"
#include <util/logging.h>

#include <elfio/elfio.hpp>
#include <iss/arch/rv64ia.h>

#ifdef __cplusplus
extern "C" {
#endif
#include <ihex.h>
#ifdef __cplusplus
}
#endif
#include <fstream>
#include <cstdio>
#include <cstring>

using namespace iss::arch;

rv64ia::rv64ia() {
    reg.icount=0;
}

rv64ia::~rv64ia(){
}

void rv64ia::reset(uint64_t address) {
    for(size_t i=0; i<traits<rv64ia>::NUM_REGS; ++i) set_reg(i, std::vector<uint8_t>(sizeof(traits<rv64ia>::reg_t),0));
    reg.PC=address;
    reg.NEXT_PC=reg.PC;
    reg.trap_state=0;
    reg.machine_state=0x0;
}

uint8_t* rv64ia::get_regs_base_ptr(){
    return reinterpret_cast<uint8_t*>(&reg);
}

rv64ia::phys_addr_t rv64ia::v2p(const iss::addr_t& pc) {
    return phys_addr_t(pc); //change logical address to physical address
}