DBT-RISE-TGC/platform/gen_input/uart.rdl

regfile uart_regs {
	reg {
		name="txdata";
		desc="Transmit data register";
		field {} data[7:0];
		field {} full[31:31];
	} txdata @0x00;
	reg {
		name="rxdata";
		desc="Receive data register";
		field {} data[7:0];
		field {} empty[31:31];
	}rxdata @0x04;
	reg {
		name="txctrl";
		desc="Transmit control register";
		field {} txen[1];
		field {} nstop[1];
		field {} txcnt[18:16];
	}txctrl @0x08;
	reg {
		name="rxctrl";
		desc="Receive control register";
		field {} rxen[1];
		field {} rxcnt[18:16];
	}rxctrl @0x0C;
	reg {
		name="ie";
		desc="UART interrupt enable";
		field{} txwm[1];
		field{} rxwm[1];
	}ie @0x10;
	reg {
		name="ip";
		desc="UART Interrupt pending";
		field{} txwm[1];
		field{} rxwm[1];
	} ip @0x14;
	reg {
		name="div";
		desc="Baud rate divisor";
		field{} div[16];
	} div @0x18;
};